Multiphase PWM Signal Generator for Fine Duty Cycle Resolution
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Solution Overview
Problem
Existing PWM signal generation methods face limitations in accuracy and resolution due to clock frequency constraints, particularly in high-frequency applications where precise control of duty cycle is necessary to minimize power consumption and noise levels.
Innovation Solution
A PWM signal generator circuit utilizing a multiphase clock generator to produce phase-shifted clock phases, allowing for precise control of switch-on and switch-off durations by combining integer clock periods with fractional periods, thereby enhancing resolution and accuracy of the PWM signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a digital implementation using clock signal and counter is used to generate PWM signal, then the circuit structure is simple, but the accuracy and resolution of the PWM signal is limited by the clock period
Solution Approach 1:
The PWM period is segmented into multiple phases (e.g., 5 phases), with each phase representing a fraction (1/5) of the total period. This segmentation allows the PWM duty cycle to be controlled with finer granularity by combining integer clock periods with fractional phase shifts, thereby improving resolution without requiring a higher clock frequency.
2Measurement precision
If the clock frequency is increased to improve PWM signal resolution, then the accuracy and resolution improve, but the switching losses increase
Solution Approach 1:
The PWM period is segmented into multiple phases (e.g., 5 phases), with each phase representing a fraction (1/5) of the total period. This segmentation allows the PWM duty cycle to be controlled with finer granularity by combining integer clock periods with fractional phase shifts, thereby improving resolution without requiring a higher clock frequency.
3Measurement precision
If multiple clock phases are used to generate high resolution PWM signal, then the PWM signal resolution improves, but the device complexity increases
Solution Approach 1:
Multiple phase-shifted clock phases are combined through a logic circuit (e.g., OR gate) to generate the final PWM signal. The merging process integrates the fractional time control from different phases with the integer clock period control, achieving high resolution PWM output while maintaining a relatively simple overall circuit structure.
4Volume of moving object
If small inductors are used to miniaturize equipment, then the equipment size is reduced, but a high-frequency modulated waveform PWM signal with high precise resolution is required to keep power consumption at acceptable values
Solution Approach 1:
The PWM period is segmented into multiple phases (e.g., 5 phases), with each phase representing a fraction (1/5) of the total period. This segmentation allows the PWM duty cycle to be controlled with finer granularity by combining integer clock periods with fractional phase shifts, thereby improving resolution without requiring a higher clock frequency.
Data Source
AI summary
A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.