Multiplane Flash Erase Testing to Isolate Slow Blocks
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Solution Overview
Problem
Multiplane erase processes in non-volatile memory systems can fail due to defects in one plane, marking all blocks as bad and causing unnecessary retirement, leading to capacity loss.
Innovation Solution
Implement a multiplane erase process with a test for defective blocks, excluding potentially defective groups from the erase operation to prevent unnecessary retirement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiplane erase is performed concurrently on multiple planes, then erase speed is improved, but reliability deteriorates due to neighbor plane disturb causing false defects
Solution Approach 1:
The patent applies preliminary action by performing a test erase operation on a subset of blocks before the full multiplane erase. This test phase identifies blocks that are susceptible to neighbor plane disturb, allowing the system to create a exclude list of problematic blocks before committing to the full erase operation, thus preventing false defect markings.
Solution Approach 2:
The patent segments the erase operation into multiple phases: a test erase phase on a subset of blocks, followed by a full erase phase. It also segments the block set into includable blocks and excludable blocks based on test results. This segmentation allows reliable identification of problematic blocks while maintaining overall erase efficiency.
2Reliability
If all blocks are marked as bad when one block fails erase, then reliability is maintained, but capacity is lost due to unnecessary retirement
Solution Approach 1:
The patent applies local quality by treating each block individually based on its specific erase test results rather than applying a uniform mark-bad status to all blocks. Blocks that pass the test erase are identified as having good erase characteristics and are retained, while only the specific blocks that fail the test are excluded. This localized assessment preserves memory capacity while maintaining data integrity.
Solution Approach 2:
The patent implements feedback by using the results of test erase operations to dynamically determine which blocks should be included or excluded from the full erase operation. The system learns from test results and adjusts the erase strategy accordingly, preventing false defect markings while ensuring reliable erasure of problematic blocks.
3Measurement precision
If test erase is performed on all blocks before full erase, then defect detection accuracy is improved, but erase time increases
Solution Approach 1:
The patent applies partial action by performing test erase operations on only a subset of blocks (e.g., one block per plane or a representative sample) rather than all blocks. This partial testing provides sufficient information to identify neighbor plane disturb susceptibility patterns, allowing the system to make informed decisions about which blocks to exclude without the time cost of testing every single block.
Data Source
AI summary
A non-volatile memory system is configured to perform a multiplane erase process that concurrently erases groups of memory cells in multiple planes. Based on that multiplane erase process, the memory system determines that a first group of memory cells in a first plane of the multiple planes is slow to erase. As a result, the system will perform one or more multiplane erase processes for the groups of memory cells in multiple planes without erasing the first group of memory cells in the first plane as part of the multiplane erase process(es).