Multiple Gate Transistor Fin Patterning Without Epitaxial Growth
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Solution Overview
Problem
The fabrication of advanced integrated circuits using multiple gate transistors faces challenges in achieving high throughput due to the requirement of epitaxial growth processes, which are complex and reduce manufacturing efficiency, especially in forming continuous drain and source areas.
Innovation Solution
The method involves forming fins in a spatially restricted area defined by a mask material, using a placeholder structure to create drain and source areas, and then patterning the semiconductor layer to form the fins without epitaxial growth, allowing for a self-aligned and efficient manufacturing process that avoids complex epitaxial growth techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epitaxial growth processes are used to form continuous drain and source areas in multiple gate transistors, then the transistor structure and performance are improved, but the manufacturing complexity and process time increase significantly
Solution Approach 1:
The patent applies preliminary action by forming placeholder structures that define the future drain and source regions before fin formation. These placeholders are created in advance using standard lithography and deposition, allowing the epitaxial growth to occur in predetermined locations without requiring complex real-time process control during fin formation.
Solution Approach 2:
The patent segments the drain and source region formation into distinct stages: first creating placeholder structures, then using them as masks during selective epitaxial growth to form continuous drain and source areas. This segmentation allows each step to be optimized independently and simplifies the overall process control.
2Reliability
If epitaxial growth processes are used to form continuous drain and source areas, then the transistor performance is improved, but the manufacturing throughput decreases
Solution Approach 1:
The patent merges multiple process functions into unified steps. The placeholder structures serve dual purposes as both definition templates and masks for epitaxial growth. Additionally, the gate electrode formation is integrated with the fin patterning process, reducing the total number of separate fabrication steps and improving throughput.
Solution Approach 2:
The placeholder structures are designed to be self-aligning and self-defining for the subsequent epitaxial growth process. The structures automatically define the drain and source region boundaries without requiring additional alignment steps or complex process control, allowing the process to proceed efficiently with standard equipment.
3Manufacturing precision
If complex epitaxial growth techniques are used for forming drain and source areas, then the continuous drain and source regions are achieved, but the ease of manufacture is reduced
Solution Approach 1:
The patent introduces placeholder structures as intermediary elements that mediate between the lithography step and the epitaxial growth step. These placeholders translate the pattern from the lithography layer into precise definitions for the drain and source regions during epitaxial growth, ensuring manufacturing precision while using standard, well-understood processes.
Solution Approach 2:
The patent utilizes parameter changes in the epitaxial growth process, specifically controlling the growth conditions to achieve selective formation of continuous drain and source regions only in the areas defined by the placeholder structures. This allows precise control over the formation of continuous regions without requiring complex process equipment.
Data Source
AI summary
The drain and source regions of a multiple gate transistor may be formed without an epitaxial growth process by using a placeholder structure for forming the drain and source dopant profiles and subsequently masking the drain and source areas and removing the placeholder structures so as to expose the channel area of the transistor. Thereafter, corresponding fins may be patterned and a gate electrode structure may be formed. Consequently, reduced cycle times may be accomplished due to the avoidance of the epitaxial growth process.