Multiple Select Gate Architecture With Different Lengths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As flash memory device sizes decrease, issues such as increased leakage current and program disturb arise due to gate-induced drain leakage (GIDL), which can lead to unintended programming of unselected cells during programming operations, and punch-through remains a concern even with multiple select gates.
Innovation Solution
The implementation of a multiple select gate architecture where source and drain select gates have different lengths, reducing GIDL by adjusting channel voltages and lengths to inhibit programming of unselected cells and minimizing punch-through during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device size is decreased to increase memory density, then memory density is improved, but leakage current increases
Solution Approach 1:
The select gate is divided into multiple segmented gates (first select gate and second select gate) along the channel length. This segmentation allows each gate to be optimized independently, with the first gate having a shorter length to reduce GIDL and the second gate having a longer length to provide sufficient blocking capability, thereby reducing overall leakage current while maintaining high memory density
Solution Approach 2:
Different regions of the select gate structure are assigned different gate lengths tailored to their specific functional requirements. The first select gate region uses a shorter length optimized for reducing GIDL in high-density areas, while the second select gate region uses a longer length optimized for blocking leakage current, achieving local optimization of the harmful effects without compromising overall device performance
2Quantity of substance
If channel length is reduced to increase memory density, then memory density is improved, but GIDL increases
Solution Approach 1:
The select gate is segmented into multiple gates with different lengths. The first select gate has a shorter channel length optimized to reduce GIDL effects, while the second select gate has a longer channel length to provide adequate blocking. This segmentation allows the first gate to minimize GIDL generation while the second gate ensures sufficient current blocking, enabling high memory density without excessive GIDL
Solution Approach 2:
The gate length parameter is varied along the channel direction, with the first select gate having length L1 and the second select gate having length L2 where L1 < L2. This parameter change optimizes the balance between GIDL reduction (shorter gate) and blocking capability (longer gate), allowing high memory density while controlling GIDL effects
3Object-generated harmful factors
If multiple select gates are used to reduce GIDL, then leakage current is reduced, but punch-through risk remains
Solution Approach 1:
Different select gate regions are assigned different lengths based on their local functional requirements. The first select gate uses a shorter length optimized for GIDL reduction where GIDL is most problematic, while the second select gate uses a longer length optimized for preventing punch-through where higher blocking is needed, achieving both leakage reduction and punch-through protection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces GIDL and minimizes the risk of program disturb and punch-through, enhancing the reliability and performance of flash memory devices by controlling channel voltages and lengths of select gates.
Implementation Method 1
gate induced drain leakage (GIDL) that results from the depletion at the drain surface below the gate-drain overlap region
Implementation Method 2
during a read operation punch-through may still be a concern even with multiple select gates
Data Source
AI summary
The invention provides methods and apparatus. A portion of a memory array has a string of two or more non-volatile memory cells, a first select gate coupled in series with one non-volatile memory cell of the string of two or more non-volatile memory cells, and a second select gate coupled in series with the first select gate. A length of the second select gate is greater than a length of the first select gate.