Multiple Select Gate Architecture for NAND Memory Leakage Control
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Solution Overview
Problem
As flash memory devices shrink in size, they face increased leakage currents, particularly gate-induced drain leakage (GIDL), which can lead to program disturb issues, necessitating larger select transistors that counteract the desire for smaller memory array sizes.
Innovation Solution
Implementing multiple series-coupled select gates on the drain and/or source ends of NAND strings allows for smaller feature sizes while maintaining protection against leakage currents, reducing the memory device footprint by using smaller select gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory array size is decreased to improve memory density, then memory density increases, but leakage current increases due to reduced channel length and gate oxide thickness
Solution Approach 1:
The patent divides a single select gate into multiple series-coupled select gates (first select gate and second select gate) positioned at different ends of the NAND string. This segmentation allows each individual gate to have smaller dimensions while collectively providing sufficient protection against leakage current, thereby enabling reduced memory array size without compromising leakage control.
2Reliability
If the gate length of select transistors is increased to mitigate GIDL and prevent program disturb, then protection against leakage current improves, but memory array size increases
Solution Approach 1:
Instead of using a single long select gate, the patent employs multiple shorter select gates in series. The first select gate and second select gate are positioned at opposite ends of the NAND string, with each having a manageable gate length that provides adequate GIDL protection while keeping individual gate dimensions small, thus reducing overall memory array footprint.
Solution Approach 2:
The patent utilizes the spatial dimension by positioning select gates at both ends of the NAND string rather than relying on a single gate spanning the entire length. This dimensional approach allows each gate to be smaller while collectively covering the necessary protection distance, effectively reducing the area required for select gates in the memory array.
Data Source
AI summary
Non-volatile memory devices including multiple series-coupled select gates on the drain and/or source ends of strings of non-volatile memory cells. By utilizing multiple series-coupled select gates, each gate can be made using smaller features sizes while achieving the same level of protection against GIDL and other forms of current leakage. By reducing the feature size of the select gates, the footprint of the strings of memory cells can be reduced, thereby facilitating smaller memory device sizing. Further reductions in device sizing may be achieved utilizing a staggered self-aligned bit line contact configuration.