Multiplexed Oscillator Clock Switching for Frequency Drift Tolerance
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Solution Overview
Problem
Existing integrated circuit devices with multiplexed oscillators face challenges in detecting excessive fluctuations in oscillation frequency over long-term operation, which is not adequately addressed by current technologies using two oscillators, as they cannot handle frequency rises or drops effectively.
Innovation Solution
An integrated circuit device with two oscillators that compares and monitors the frequencies of the clock signals, selecting the output clock signal based on frequency tolerance ranges, and switches between them to maintain operational stability, even when one oscillator's frequency deviates, thereby handling fluctuations and reducing the number of oscillators required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If three or more oscillators are used for multiplexing to detect abnormalities and maintain operation, then functional safety is improved, but device complexity and circuit scale increase
Solution Approach 1:
The patent combines multiple oscillator circuits into a single integrated oscillator block that generates multiple clock signals internally. Instead of using three separate oscillator circuits, the invention integrates them share a common structure with selective activation, reducing overall circuit scale while maintaining the functional safety benefits of having multiple oscillators for abnormality detection and standby operation.
Solution Approach 2:
The patent creates a universal oscillator circuit that can function as both the primary operation clock source and the standby clock source depending on activation state. The oscillator circuit is designed to be multi-functional, serving different roles (normal operation vs. abnormality standby) without requiring separate dedicated circuits for each function, thereby reducing device complexity.
2Device complexity
If two oscillators are used for multiplexing with operation clock and standby clock, then device complexity is reduced, but the ability to detect excessive frequency fluctuations is lost
Solution Approach 1:
The patent implements frequency detection circuits that continuously monitor the clock signals generated by the oscillators. When an abnormality is detected in the operation clock frequency, the system provides feedback to switch to the standby clock. This feedback mechanism enables precise frequency monitoring and automatic correction, maintaining measurement precision while using only two oscillators.
Solution Approach 2:
The patent prepares a standby clock circuit in advance that mirrors the operation clock circuit's functionality. This preliminary preparation of the standby system allows for immediate switching when frequency abnormalities are detected, without requiring additional oscillators. The standby circuit is pre-configured to take over if the primary oscillator drifts outside tolerance ranges.
3Productivity
If oscillators are used for long-term operation, then productivity is maintained, but frequency drift occurs causing operational instability
Solution Approach 1:
The patent implements a dynamic clock selection system that can switch between operation clock and standby clock based on real-time frequency monitoring. This dynamic adaptation allows the system to maintain stable operation even during long-term use by automatically replacing drifted oscillators with fresh standby oscillators, thereby maintaining both productivity and frequency stability over extended periods.
Solution Approach 2:
The patent changes the operational state parameters of the oscillator system by introducing frequency tolerance thresholds and automatic switching mechanisms. When oscillation frequency parameters drift beyond acceptable ranges due to long-term operation, the system automatically changes state from using the degraded oscillator to using a fresh standby oscillator, maintaining operational stability throughout the device lifecycle.
Data Source
AI summary
An integrated circuit device contains two oscillators to generate a first clock signal and a second clock signal. Along with comparing the frequencies of the first clock signal and the second clock signal, the integrated circuit device is configured to monitor whether or not each frequency is within the frequency tolerance range. The integrated circuit device selects an output clock signal from either of the first clock signal or the second clock signal according to results from comparing the frequencies of the first clock signal and the second clock signal and whether or not each of the first clock signal and the second clock signal are within the frequency tolerance range.