Multiplexed Sigma-Delta ADC Clocking to Prevent Channel Data Mixing
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Solution Overview
Problem
Higher-order sigma-delta analog-to-digital converters (ADCs) face challenges in channel multiplexing due to the incorrect mixing of sampled data when multiple channels are processed, especially with two delaying integrators, which limits bandwidth and noise reduction capabilities.
Innovation Solution
The implementation of a multiplexed sigma-delta ADC with two delaying integrators and a non-delaying integrator, using distinct clock sets for each integrator stage to prevent data mixing, along with advanced clocking principles and local feedback mechanisms, allows for correct channel multiplexing and improved noise shaping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple delaying integrators are used in higher-order SDADC to improve noise reduction and bandwidth, then noise levels are reduced and bandwidth is increased, but channel multiplexing becomes incorrect and data mixing occurs
Solution Approach 1:
The patent divides the integrator chain into two separate groups: delaying integrators (first, third, fifth stages) and non-delaying integrators (second, fourth stages). Each group is controlled by distinct clock sets with different phase relationships, preventing data mixing while maintaining noise reduction benefits. The channel selection clocks for delaying integrators are phased differently than those for non-delaying integrators, ensuring correct channel assignment.
Solution Approach 2:
The patent implements dynamic clocking where the phase relationship between channel selection clocks varies depending on the integrator stage. Delaying integrators use channel selection clocks with one phase relationship, while non-delaying integrators use clocks with a different phase relationship. This dynamic adjustment of timing parameters allows the system to maintain correct channel multiplexing across all integrator stages.
2Speed
If multiple delaying integrators are used in higher-order SDADC to increase bandwidth, then bandwidth is increased, but data from consecutive full clock cycles becomes mixed
Solution Approach 1:
The patent segments the integrator chain into delaying and non-delaying groups, each with dedicated clock sets. This segmentation ensures that samples from different clock cycles are routed to the correct integrator stage, preventing data mixing while allowing the system to operate at higher bandwidths with multiple delaying integrators.
Solution Approach 2:
The patent introduces non-delaying integrators as intermediary stages between delaying integrators. These non-delaying integrators act as buffer stages that receive samples at one timing phase and output to the next delaying integrator at a different timing phase, preventing direct data mixing between consecutive clock cycles while maintaining the bandwidth benefits of multiple delaying integrators.
3Measurement precision
If higher-order quantizer is used to reduce noise, then noise levels are reduced, but nonlinearity risk increases
Solution Approach 1:
The patent segments the noise reduction function across multiple integrator stages rather than relying on a single high-order quantizer. By distributing the noise shaping across first, second, third, fourth, and fifth integrators with appropriate clocking, the system achieves noise reduction while maintaining the simplicity and linearity of 1-bit or low-order quantizers.
Data Source
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AI summary
The present invention relates to a multiplexed sigma-delta analog-to-digital converter, ADC, for digitizing analog input signals of at least two input channels. The ADC comprises input circuitry configured to obtain samples of said at least two input channels and an integrator chain. The integrator chain comprises a first delaying integrator and a second delaying integrator. The first delaying integrator is configured to process a sample of one of said at least two input channels at a time. A first non-delaying integrator is disposed in the integrator chain between the first delaying integrator and the second delaying integrator, or after the second delaying integrator. Clocking arrangement comprises first clock set and a second clock set. Channel selection clocks comprised in the second clock set are delayed in comparison to the respective channel selection clocks comprised in the first clock set for preventing data from being mixed between consecutive full clock cycles.