Analogue Conversion TRIZ Cases

Overlap processing reuses boundary samples across parallel delta-sigma blocks to cut calculation errors in high-speed digital signal processing.

Sigma-delta encoding and feedback noise cancellation cut DAC bit depth and sampling demands while preserving multichannel transmitter linearization.

Series-connected analogue gain stages extend audio input gain range for guitars and low-gain microphones while preserving signal quality.

An up/down counter with delta adders restores full delta-sigma bit-stream amplitude after one-half attenuation using simple low-power logic.

Digital dithering added after the quantizer breaks sigma-delta loop periodicity to suppress idle tones without analog-domain saturation.

A reference voltage compensator uses ADC digital output feedback to suppress voltage fluctuation and improve THD during conversion.

Parallel inductors across integrator input resistors widen low-frequency integral behavior and protect signal-to-quantization noise ratio.

Digitally trimmed charge injection cancels sigma-delta input current, improving differential voltage sensing under high common-mode voltage.

A multiplexed delta-sigma path converts DC and AC analog signals through one modulation circuit, reducing separate signal-chain complexity.

Bit-sliced PWM shortens analog crossbar integration time while preserving multi-bit accuracy through scaled partial-result accumulation.

Dynamically selectable resistors let a programmable gain amplifier sample beyond-rail voltages without dividers, cutting current use and hardware.

Multiple biased transistor sensing circuits and a delta-sigma ADC cut low-frequency sensor noise, improving close-in phase noise in TCXOs.

An external analog chopper and digital demodulator cut offset, low-frequency noise, and ΣΔ loop complexity in sensor conversion.

Noise-shaped dither shifts ADC dither energy above a cutoff frequency to cut near-tone phase noise while improving SFDR and preserving SNR.

A receiver circuit selects among analog inputs so one delta-sigma ADC can cut converter count, cost, and complexity while retaining fast output generation.

Copies parasitic capacitance into the ADC feedback path to boost input impedance without trimming, extra calibration, or added power.

Equalizing node voltages in a sampling circuit preserves ADC linearity under leakage current and temperature-driven on-resistance changes.

High-order polynomial interpolation preserves amplitude and phase during carrier frequency changes, reducing phased-array signal errors and latency.

A VCO-based Delta-Sigma ADC moves Class-D amplifier error processing into the digital domain, improving modulation accuracy and fabrication reliability.

Hardware channel comparison with threshold-count timing detects insulated ADC signal errors and reduces software safety processing.

A DC rejection path cancels offset in the high-frequency sensor channel, enabling accurate wide-band magnetic field measurement without large decoupling capacitors.

Phase alignment between startup control signals smooths closed-loop Class-D amplifier transition and reduces spurious input noise.

A low-resistance reset bypass speeds parasitic capacitance discharge in an RTO DAC, reducing data dependency and ADC distortion.

A cascaded VCO-based ADC cancels quantizer nonlinearity with an error-correction stage to improve SNR, bandwidth, and low-power operation.

An on-chip FIR DAC turns digital reference data into an analog test signal, enabling accurate CTDS ADC validation without external test gear.

A punctured quantizer limits SNDR saturation to cut ADC power and chip area while preserving wide dynamic range for battery-operated IoT devices.

Auxiliary current is switched in only when needed to keep the integrator output valid, cutting power while improving low-noise settling.

A pressure sensor readout uses auto-zeroing and switched-capacitor sampling to suppress water-droplet parasitic capacitance errors.

Oversampling and noise shaping digitize multiple RAT carriers with two or fewer bits, improving fronthaul spectral efficiency and reducing RRH complexity.

Analog and digital signal comparison detects ADC faults without full redundancy, supporting functional safety in sensor circuits.

Multiple injection and feedback branches let one sigma-delta ADC handle voltage, capacitance, and current inputs with lower area and power.

Auto-zeroing and out-of-phase offset capacitance suppress water-droplet parasitics, preserving accurate pressure sensor readout.

A SAR first stage and VCO residue quantizer achieve second-order noise shaping while mitigating VCO non-linearity and harmonic distortion.

Integrating the C2V converter into a bandpass sigma-delta ADC cuts temperature-driven delay mismatch and ADC offset non-linearity in MEMS gyroscopes.

Delayed channel-selection clocks and a non-delaying integrator prevent data mixing in higher-order multiplexed sigma-delta ADCs.

A delayed error-feedback gated ring oscillator ADC adds second-order noise shaping to cut power use while preserving high bandwidth and resolution.

Selective out-of-band frequency amplification in a delta-sigma modulator suppresses quantization noise without sacrificing in-band noise reduction.

Compensation for leakage-induced reference droop keeps shared-reference delta-sigma converters accurate when other channels are disabled.

Reordered ring-oscillator phases with MLS and Johnson counters cut desynchronization and metastability errors in low-power ADCs.

Parasitic capacitance is copied into the ADC positive feedback path to boost input impedance without trimming, added complexity, or extra power.

A body-driven VCO quantizer, linear integrator, and 4-tap FIR feedback improve CT delta-sigma ADC linearity, bandwidth, and noise.

A chopper-based continuous-time ADC handles wide-range sensor signals without variable gain stages, cutting noise, offset, power, and chip area.

A preset loop filter keeps the quantized signal non-zero at reset, improving incremental ADC transient response and conversion accuracy.

Compensation gains correct DAC mismatch in ADC feedback paths, improving sigma-delta conversion accuracy without input shuffling.

A shared programmable Rx filter and ADC adapt bandwidth across receive and transmit modes to cut WiFi receiver power use.

Filtered sigma-delta ADC output is corrected by a neural network to improve SNDR, THD, and accuracy without extra analog circuitry.

A synchronized low-duty LED drive clock cuts photocoupler power use while preserving isolation communication reliability and LED life.

A differential and sigma-delta channel driver senses and drives one touch node at once, cutting parasitic capacitance and noise delays.

By reducing quantization levels from a delta-sigma ADC output, this circuit cuts bit transitions, easing bus throughput limits and power use.

A range detector adjusts the held voltage across input ranges, enabling seamless amplifier range switching without loop disturbance.

Adaptive digital conjugate weighting corrects frequency-dependent I/Q imbalance in quadrature receivers to cut distortion and noise.

A parallel digital RF transmitter moves up-conversion before pulse encoding to cut out-of-band noise and lower sampling demands.

Direct mapping converts single-bit audio into constant-edge-rate symbols, improving volume control while reducing playback noise and distortion.

By redistributing digital signals across weighted DAC sub-circuits, this case reduces element-mismatch noise voltage and improves SNR in oversampling converters.

A single-comparator time-interleaved quantization scheme restores delayed feedback to raise DSM speed and resolution without degrading transfer integrity.

A low-output-impedance body bias circuit tracks threshold shifts to reduce DAC leakage while preserving linearity across process and temperature changes.

A coarse and fine Sigma-Delta DAC split boosts output resolution while reducing area, power, and calibration complexity.

Dual-threshold VAD and selective spectral analysis cut always-listening current draw while keeping voice-command misdetection low.

A segmented series-parallel resistor network gives a PGA wide gain selection with lower thermal noise, die area, and power.

A PAC circuit linearizes PDM transition behavior to cancel DC offset from asymmetric I/O pads without added pad complexity, area, or power.

A delta-sigma feedback network detects overload events and resets integrators to keep class-D audio amplifiers linear and stable.