Sampling Circuit Linearization for Leakage-Resistant High-Speed ADCs
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Solution Overview
Problem
High-speed analog-to-digital converters, particularly in time-interleaved configurations, face linearity deterioration due to leakage currents and temperature variations, which affect the accuracy of sampling high-frequency signals.
Innovation Solution
Incorporating a linearization circuit within the sampling circuit that utilizes switches and capacitors to maintain linearity by equalizing voltage levels across nodes, even when on-resistance increases due to high-temperature or high-speed conditions, thereby reducing leakage current impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sampling speed is increased to achieve high-speed communication, then productivity is improved, but linearity deteriorates due to process, temperature and voltage variations
Solution Approach 1:
The patent applies equipotentiality by connecting the first and second nodes to the same potential through the linearization circuit. This ensures that voltage variations and leakage currents do not create potential differences between nodes, thereby maintaining linearity between input and output signals even at high sampling speeds where such variations become significant
2Productivity
If temperature increases due to high-speed operation, then productivity is improved, but linearity deteriorates due to increased on-resistance
Solution Approach 1:
The linearization circuit maintains equipotential conditions between nodes despite temperature-induced resistance changes. By ensuring both nodes remain at the same potential, the circuit compensates for increased on-resistance effects, preserving signal linearity during high-speed operation that generates heat
3Productivity
If leakage current increases under challenging conditions, then productivity is improved, but measurement precision deteriorates
Solution Approach 1:
The patent eliminates the impact of leakage currents on measurement precision by maintaining equipotential conditions. When both nodes are at the same potential, leakage currents flowing through the switches do not create voltage drops or signal errors, ensuring accurate sampling even when leakage increases due to temperature or process variations
Data Source
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Figure 3A
AI summary
A sampling circuit includes a linearization circuit connected to a first input terminal for receiving a first input signal and a second input terminal for receiving a second input signal, a first switch connected between the first input terminal and the linearization circuit, a second switch connected between the first input terminal and the linearization circuit, a third switch connected between the second input terminal and the linearization circuit, a fourth switch connected between the second input terminal and the linearization circuit, a first capacitor connected between the linearization circuit and a first output terminal for outputting a first sampled signal, and a second capacitor connected between the linearization circuit and a second output terminal for outputting a second sampled signal.