Vector-Quantized DAC Architecture for Oversampling Noise Suppression
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Solution Overview
Problem
Conventional digital-to-analog converters in oversampling converters face accuracy and performance issues due to element mismatch, leading to noise voltage and reduced signal quality, which existing data weighted averaging techniques partially address but not fully resolve.
Innovation Solution
A vector quantization digital-to-analog conversion circuit that includes a quotient calculator, remainder calculator, quantization circuit, loop circuit, and data weighted averaging circuit to generate a vector quantization signal, increasing entropy and reducing noise voltage by allocating digital signals across multiple sub-signal paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional data weighted averaging technique is used to improve element mismatch, then conversion accuracy is improved, but noise voltage is generated due to repetition of selected elements
Solution Approach 1:
The patent implements dynamic element selection through data weighted averaging, where the selection of interior elements changes over time based on input data patterns. This dynamic approach prevents fixed repetition of the same elements, thereby reducing noise voltage while maintaining conversion accuracy through adaptive element utilization.
Solution Approach 2:
The patent changes the weighting parameters assigned to different interior elements based on their mismatch characteristics. By dynamically adjusting these weights, the system optimizes conversion accuracy while distributing element usage to minimize noise generation from repetitive selections.
2Object-generated harmful factors
If extra elements are added to perform data weighted averaging, then element mismatch noise is reduced, but element quantity increases
Solution Approach 1:
The patent segments the interior elements into multiple groups and applies different weighting strategies to each group. This segmentation allows the system to manage element utilization more efficiently, reducing mismatch noise through diversified element selection without requiring a proportional increase in total element quantity.
Solution Approach 2:
The patent makes existing interior elements serve multiple functions by dynamically reassigning their roles and weights based on input conditions. This multi-functionality approach allows the same set of elements to handle various conversion scenarios effectively, reducing the need for additional elements while maintaining noise performance.
3Object-generated harmful factors
If repetition of selected elements is reduced, then noise voltage is reduced, but conversion complexity increases
Solution Approach 1:
The patent performs preliminary classification and weighting assignment to interior elements before the actual conversion process. By pre-establishing element groups and their weightings based on mismatch characteristics, the system reduces noise voltage through controlled element selection without requiring complex real-time decision-making during conversion.
Solution Approach 2:
The patent implements feedback mechanisms that monitor element selection patterns and adjust weighting assignments accordingly. This feedback loop enables the system to reduce noise voltage by learning from past selections and adapting element utilization strategies, managing complexity through iterative optimization rather than rigid complex structures.
Data Source
AI summary
The application provides a vector quantization digital-to-analog conversion circuit, applied to an oversampling converter, characterized that the vector quantization digital-to-analog conversion circuit includes a vector quantization circuit, configured to generate a vector quantization signal, a data weighted averaging circuit, coupled to the vector quantization circuit, including a plurality of data weighted averaging sub-circuits, configured to receive the vector quantization signal to generate a plurality of data weighted averaging signals; and a digital-to-analog conversion circuit, coupled to the data weighted averaging circuit, including a plurality of digital-to-analog conversion sub-circuits, configured to receive the data weighted averaging signal to generate the analog signal.