Cascaded VCO-Based ADC for Nonlinearity Cancellation and High SNR
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs) face challenges in high silicon area usage, power consumption, and achieving sufficient signal-to-noise ratio (SNR) and conversion bandwidth, especially in low voltage and low power deep submicron processes, due to limitations in Delta-Sigma ADC methods and VCO quantizer non-linearity.
Innovation Solution
A cascaded VCO-Based Delta-Sigma ADC is introduced, combining a VCO-Based Delta-Sigma ADC loop with a forward path quantizer to cancel VCO quantizer nonlinearity, utilizing a first ADC stage with a VCO and a second ADC stage to remove harmonic distortion and improve noise shaping, while employing a digital filter to align and decimate signals for enhanced SNR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a VCO quantizer is used in the ADC, then conversion bandwidth is improved, but VCO quantizer non-linearity introduces harmonic distortion and reduces signal-to-noise ratio
Solution Approach 1:
The patent applies noise shaping to deliberately push quantization noise to higher frequencies where it can be filtered out, converting the harmful quantization noise into a manageable form. The VCO quantizer's non-linearity is compensated through digital signal processing that shapes the noise spectrum, allowing the system to maintain high conversion bandwidth while improving signal-to-noise ratio in the band of interest.
2Measurement precision
If Delta-Sigma ADC methods are used, then signal-to-noise ratio is improved through noise shaping, but conversion bandwidth is limited and power consumption increases
Solution Approach 1:
The patent changes the operating parameters of the ADC by using a VCO-based quantizer instead of a traditional multi-bit quantizer. This parameter change allows the system to achieve both high signal-to-noise ratio through noise shaping and high conversion bandwidth through the VCO's inherent frequency modulation capability, while reducing power consumption by operating in deep submicron processes optimized for low voltage.
3Use of energy by stationary object
If deep submicron processes are used for low voltage and low power operation, then power consumption is reduced, but achieving sufficient SNR and conversion bandwidth becomes more difficult
Solution Approach 1:
The patent replaces traditional high-power analog filtering and amplification mechanisms with digital signal processing techniques. By using digital noise shaping and filtering in the baseband, the system achieves sufficient signal-to-noise ratio without requiring high-power analog components, enabling low voltage and low power operation in deep submicron processes while maintaining performance.
Data Source
AI summary
An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input signal. A first ADC circuit is coupled to the input terminal and includes a VCO. The first ADC circuit is configured to output a first digital signal in a frequency domain based on the analog input signal. The first digital signal includes an error component. A first DAC is configured to convert the first digital signal to an analog output signal. A first summation circuit is configured to receive the analog output signal, the analog input signal, and a loop filtered version of the analog input signal and extract the error component, and output a negative of the error component. A second ADC circuit is configured to convert the negative of the error component to a digital error signal. A second summation circuit is configured to receive the first digital signal and the digital error signal, and to output a digital output signal corresponding to the analog input at an output terminal.