Sub-Ranging Current-Mode DAC With Sigma-Delta Paths for High Resolution
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Solution Overview
Problem
High-resolution Digital-to-Analog Converters (DACs) face challenges in achieving efficient area and power usage while maintaining monotonicity and requiring complex calibration, especially in high-resolution designs where mismatch errors and glitches are prevalent.
Innovation Solution
A sub-ranging current mode DAC design utilizing two 1-bit Sigma-Delta (ΣΔ) encoded bitstreams, where a coarse DAC and a fine DAC are combined using nth order and 1st order ΣΔ modulators respectively, with a Low Pass Filter to produce a high-resolution output, allowing for efficient area and power usage and simplified calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-resolution DAC designs are implemented, then output resolution is improved, but area occupancy and power consumption increase
Solution Approach 1:
The patent divides the high-resolution DAC into multiple segmented paths, each handling a portion of the resolution. Specifically, it uses multiple 1-bit DACs in parallel with Sigma-Delta modulators to achieve high effective resolution without requiring a single large-scale DAC structure, thereby reducing area occupancy while maintaining high resolution output.
Solution Approach 2:
The patent transitions from a single-dimensional high-resolution DAC approach to a multi-dimensional architecture by combining multiple 1-bit DACs with Sigma-Delta modulation in the time domain. This dimensional shift allows achieving high resolution through temporal oversampling and noise shaping rather than spatial multiplication of DAC elements.
2Measurement precision
If high-resolution DAC designs are implemented, then output resolution is improved, but power consumption increases
Solution Approach 1:
The patent segments the high-resolution conversion task across multiple low-power 1-bit DACs operating in parallel. Each 1-bit DAC consumes minimal power, and when combined with Sigma-Delta modulation that spreads quantization noise over a wider bandwidth, the system achieves high effective resolution with lower total power consumption compared to traditional high-resolution DAC architectures.
Solution Approach 2:
The patent employs periodic Sigma-Delta modulation at oversampled rates to achieve high resolution. By using periodic switching and noise shaping over multiple cycles, the system accumulates precision over time without requiring high instantaneous power, thus reducing overall power consumption while maintaining high output resolution.
3Area of stationary object
If binary weighted DAC architecture is used, then area occupancy is reduced, but monotonicity and linearity deteriorate due to mismatch errors
Solution Approach 1:
The patent segments the binary-weighted elements into multiple groups, each handled by separate 1-bit DACs with independent Sigma-Delta modulators. This segmentation distributes the mismatch errors across multiple paths rather than concentrating them in a single binary-weighted structure, thereby maintaining monotonicity through the statistical averaging effect of multiple parallel paths while keeping area occupancy low.
Solution Approach 2:
The patent incorporates feedback mechanisms within the Sigma-Delta modulators that actively compensate for mismatch errors in the binary-weighted elements. The modulators continuously adjust the switching patterns to correct for element variations, ensuring monotonicity is maintained despite the area-efficient binary-weighted architecture.
4Manufacturing precision
If complex calibration is performed, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the calibration process into simple per-path adjustments for each 1-bit DAC path rather than requiring complex system-wide calibration. Each segmented path can be independently calibrated with minimal interaction with other paths, dramatically reducing calibration complexity while maintaining high manufacturing precision through the inherent redundancy of multiple parallel paths.
Data Source
AI summary
A X-bit Digital-to-Analog Converter (DAC) circuit includes an effective X/2-bit coarse DAC configured to produce a coarse bitstream (CBS) from a digital input DC1 using an nth order Sigma-Delta (ΣΔ) modulator, and to provide a coarse current source based on the CBS, wherein X is an even integer and n is an integer; an effective X/2-bit fine DAC configured to produce a fine bitstream (FBS) from a digital input DC2 using a 1st order ΣΔ modulator, and to provide a fine current source based on the FBS; and an output configured to form a voltage from the combination of the coarse current source and the fine current source.