2:1 Multiplexer Chain Layout for Balanced Delay Oscillation Control
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Solution Overview
Problem
Existing random number generators based on delay lines suffer from unpredictable stopping points due to imbalance between rise and fall times, making it difficult to ensure sufficient oscillations for randomness, particularly in noise environments.
Innovation Solution
The design incorporates symmetrical and asymmetrical delay lines with paired inverters to achieve balanced rise and fall times, allowing for controllable oscillation duration and improved randomness by using arithmetic sequences to determine the number of oscillations before the generator stops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional delay lines are used in random number generators, then the circuit can generate oscillations, but the rise and fall times are imbalanced making the stopping point unpredictable
Solution Approach 1:
The patent applies asymmetry by introducing asymmetrical delay elements that deliberately create different delay characteristics for rising and falling edges. These asymmetrical elements are designed to compensate for the inherent imbalances in conventional delay lines, ensuring that the total delay for high-to-low transitions matches the total delay for low-to-high transitions through careful selection of asymmetrical delay values.
Solution Approach 2:
The patent changes the delay parameters by introducing asymmetrical delay elements with specific delay values that differ from conventional symmetrical delay elements. By adjusting the asymmetrical delay parameters (Td1, Td2, Td3, Td4) to satisfy specific mathematical relationships, the overall delay balance is achieved, making the stopping point predictable.
2Duration of action of moving object
If symmetrical delay lines are used to balance rise and fall times, then oscillation duration becomes controllable, but the device complexity increases
Solution Approach 1:
The patent segments the delay line into multiple sections, each containing symmetrical and asymmetrical delay elements. This segmentation allows independent control of delay characteristics in different parts of the circuit, enabling precise control over oscillation duration while maintaining modularity that limits the overall complexity increase.
Solution Approach 2:
The patent introduces controllable elements (such as switches or variable delay components) that dynamically adjust the delay characteristics based on operating conditions. This dynamic adjustment capability allows the circuit to maintain balanced rise and fall times across different oscillation durations without requiring completely different circuit configurations.
3Reliability
If multiple delay elements are added to ensure sufficient oscillations, then randomness is improved, but the device complexity and area increase
Solution Approach 1:
The patent merges the functions of multiple delay elements into a more compact configuration by using shared resources and overlapping delay paths. The symmetrical and asymmetrical delay elements are arranged to maximize their utility, allowing the same physical structures to serve multiple delay functions simultaneously, thereby reducing the total area required.
Solution Approach 2:
The patent designs delay elements that serve multiple functions: they provide both symmetrical and asymmetrical delay characteristics, participate in multiple oscillation cycles, and contribute to both delay balancing and randomness generation. This multi-functionality reduces the total number of separate components needed, thereby reducing circuit area.
Data Source
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AI summary
The invention relates to a two-to-one logic multiplexer (7), comprising: two input terminals (A, B); an output terminal (Z); a control terminal (S); and a multiple of four two-to-one unitary multiplexers (72, 74, 76, 78) connected in series, a first unitary multiplexer (72) having its inputs connected to the input terminals, a last unitary multiplexer (78) having its output connected to the output terminal and the other unit multiplexers (74, 76) having their respective inputs interconnected to the output of the preceding multiplexer in the series association, one half of the unit multiplexers being reverse driven (75) with respect to a other half.