High-Speed Multiplexer Output Interface for Floating Voltage Suppression

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Solution Overview

Problem

Current technologies do not provide an efficient mechanism to control floating voltage states in a multiplexer within a data communication path, leading to potential startup or function failures.

Innovation Solution

A modulation circuit is integrated with the multiplexer to control the output signal independently of the selection signal, creating a current path to a power supply concurrently with or prior to signal selection, thereby preventing floating voltage states.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a multiplexer is used to select one of multiple input signals based on complementary selection signals, then signal routing functionality is achieved, but floating voltage states can occur causing startup or function failure

Engineering Contradiction:
Improvesignal routing functionalityVSAvoidstartup and function reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The modulation circuit is configured to combine the input signals and control the output signal independently of the selection signal, operating concurrently with or prior to signal selection to prevent floating voltage states from occurring in the first place

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The modulation circuit acts as an intermediary that combines the input signals and provides independent control of the output signal, mediating between the multiplexer output and the final output to eliminate floating voltage states

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12206409B2Floating voltage suppression in high speed multiplexers
Publication Date: 2025.01.21 PARADE TECHNOLOGIES LTD
  • US12206409B2 patent drawing
  • US12206409B2 patent drawing
  • US12206409B2 patent drawing

AI summary

An electronic device includes two multiplexer branches, a modulation circuit, and an output interface coupled to the modulation circuit and two multiplexer branches. A first multiplexer branch generate s first output signal from a first selection signal, a first inverse signal, and a first input signal. The first inverse signal is substantially complementary to the first selection signal. A second multiplexer branch generates a second output signal from the first selection signal, the first inverse signal, and a second input signal. The modulation circuit generates a logic output signal from the first input signal and the second input signal, independently of the first selection signal and the first inverse signal. The output interface generates a multiplexed signal tracking one of the first input signal and the second input signal based on the first output signal, the second output signal, and the logic output signal.