Multiplexer Logic Co-Debugging for Processing Condition Validation

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Solution Overview

Problem

Existing technologies face challenges in addressing unexpected behavior and security concerns in logic devices due to mutual exclusion conditions where input changes occur at different times, potentially exposing protected design regions.

Innovation Solution

A computer-implemented method is provided to automatically identify multiplexer logic devices, generate verification properties, and perform formal verification to validate processing conditions, with concurrent software and hardware debugging to correct any failures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If formal verification is performed on multiplexer logic devices to validate processing conditions, then reliability and security are improved, but device complexity and verification time increase

Engineering Contradiction:

Improveprocessing condition validationVSAvoidverification system complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

A constraint generation module serves as an intermediary between the hardware description language and the formal verification engine. This module automatically generates constraints from the HDL code, eliminating the need for manual constraint creation and reducing verification system complexity while maintaining reliability

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The system performs self-verification by automatically generating verification properties and constraints from the hardware description language code itself. The multiplexer logic device validates its own processing conditions through formally verified properties derived directly from its HDL definition, reducing external verification overhead

Inventive Principle:

Principle #25Self-service

2Manufacturing precision

If automatic identification and formal verification are implemented for multiplexer logic devices, then manufacturing precision of processing conditions is improved, but loss of time for verification processes increases

Engineering Contradiction:

Improveprocessing condition accuracyVSAvoidverification time

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

Verification properties and constraints are generated in advance during the design phase from the hardware description language code, before actual device manufacturing or testing. This preliminary generation of verification artifacts enables early detection of processing condition errors without delaying production timelines

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system transforms verification parameters by converting HDL code parameters into formal verification properties and constraints. This parameter transformation automates the verification setup process, maintaining high precision while reducing manual intervention time

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12422476B2Co-debug of processing conditions of logic devices

Publication Date: 2025.09.23 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A multiplexer logic device is automatically identified in a hardware definition language of a design. One or more verification properties of the multiplexer logic device are generated to be used in validation of a selected processing condition of the multiplexer logic device. The one or more verification properties and one or more constraints obtained from software and hardware information relating to the multiplexer logic device are provided as input to a formal verification technique. Verification is performed using the formal verification technique to validate the selected processing condition. Based on the performing verification indicating a failure to comply with the selected processing condition, debugging of the multiplexer logic device is performed.