Multiplier Precoding for Fewer Wallace Tree Compression Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing multiplier architectures require a large number of compression layers in the Wallace tree, leading to increased operation time and area due to the scattered nature of the permutation array resulting from standard encoder and adder designs.
Innovation Solution
The proposed multiplier incorporates P precoders and P encoder groups, where each precoder precodes at least two bits of the second value, and each encoder group encodes the first value and the selection signal group to produce partial products, centralizing the permutation array and reducing the number of compression layers, thereby reducing the area and increasing operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard encoder and adder design is used, then the multiplication function is correctly implemented, but the permutation array becomes scattered requiring more compression layers
Solution Approach 1:
The patent applies preliminary action by performing precoding on the multiplier bits before the standard encoding process. The precoder transforms the multiplier bits X[2M:0] into a modified form that, when combined with the Booth encoder, produces a centralized permutation array pattern. This preliminary transformation ensures that the partial products are systematically distributed rather than scattered, reducing the number of compression layers needed in the Wallace tree while maintaining multiplication correctness.
2Reliability
If more compression layers are used to handle scattered permutation array, then complete multiplication is achieved, but operation time increases
Solution Approach 1:
The precoding operation performed before encoding creates a more favorable permutation array structure that requires fewer compression layers. By transforming the multiplier bits in advance through the precoder, the system reduces the depth of the Wallace tree needed to complete the multiplication, directly reducing operation time while ensuring complete multiplication through the maintained correctness of the encoding process.
3Measurement precision
If more compression layers and adders are included, then accurate multiplication result is obtained, but the area of the multiplier increases
Solution Approach 1:
The precoder performs a preliminary transformation on the multiplier bits that fundamentally changes the distribution pattern of the permutation array. This pre-processing step ensures that subsequent encoding and compression stages require fewer adders and compression layers to achieve the same multiplication accuracy, thereby reducing the overall area of the multiplier while maintaining precise multiplication results.
4Productivity
If standard Booth encoding is applied, then partial products are generated, but the permutation array shape is scattered
Solution Approach 1:
The precoding step acts as a preliminary action that modifies the multiplier bits before they enter the Booth encoding process. This pre-transformation ensures that when the Booth encoder generates partial products, they follow a centralized and regular distribution pattern rather than a scattered one, improving the shape of the permutation array while maintaining efficient partial product generation.
Data Source
AI summary
A multiplier implements multiplication of a first value and a second value, and includes P precoders, P encoder groups, and a compressor, where each precoder is configured to: precode at least two bits in the second value, to output a selection signal group; each encoder group is configured to: encode the first value and a selection signal group output by a precoder corresponding to the encoder group, to output a partial product item; the P encoder groups include a first encoder group, a first encoder of the first encoder group is configured to: encode a first selection signal group, a least significant bit in the first value, and a first sign bit, to obtain a first partial product and a first output sign bit, the first selection signal group is a selection signal group output by a first precoder, and the first precoder corresponds to the first encoder group.