Multi-port Memory Address Control Circuit for Disturbed State Testing
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Solution Overview
Problem
Existing multi-port memory technologies face challenges in creating a disturbed state for testing, as synchronizing address signals across multiple ports is difficult due to independent operation of CPUs and increased overhead from using Built In Self Test (BIST) circuits, especially in small memory capacity chips.
Innovation Solution
A multi-port memory design with independent operation modes, where the address control circuit allows simultaneous activation of word lines for a memory cell across multiple ports using a single address signal, eliminating the need for BIST circuits and reducing chip area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If BIST circuits are used to create disturbed state for testing, then test capability is improved, but chip area overhead increases
Solution Approach 1:
The patent extracts the test capability from a separate BIST circuit and integrates it into the existing address control circuit. The address control circuit is modified to detect test mode signals and generate disturbed state address patterns, eliminating the need for dedicated BIST circuitry while maintaining test functionality.
Solution Approach 2:
The address control circuit is enhanced to perform multiple functions: normal address generation during operation and disturbed state test pattern generation during testing. By adding test mode detection and address signal coordination capabilities to the existing circuit, the patent achieves multi-functionality without increasing chip area.
2Reliability
If address signals are synchronized across multiple ports for testing, then disturbed state creation is improved, but operation complexity increases
Solution Approach 1:
The patent merges the address signal generation and coordination for multiple ports into a single address control circuit. When test mode is detected, this unified circuit generates coordinated address signals for both ports simultaneously, creating the disturbed state without requiring separate control mechanisms for each port.
Solution Approach 2:
The address control circuit acts as an intermediary that receives a single test mode signal and translates it into coordinated address signals for multiple ports. This intermediary function simplifies the control interface while achieving complex multi-port coordination for disturbed state testing.
3Adaptability or versatility
If independent port operation is maintained, then operational flexibility is improved, but test synchronization difficulty increases
Solution Approach 1:
The address control circuit dynamically switches between two operational modes: normal independent port operation mode and test coordination mode. During normal operation, each port operates independently with full flexibility. During testing, the circuit transitions to coordinated address signal generation while maintaining independent data access capabilities, achieving both flexibility and synchronization.
Data Source
AI summary
A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.