Multiport Memory Emulation via Address Translation
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Solution Overview
Problem
Existing multiport memory implementations using space or time multiplexing face challenges such as increased layout space, power consumption, and decreased bandwidth, with space-multiplexing requiring larger bitcells and time-multiplexing resulting in lower frequencies and higher cycle latencies.
Innovation Solution
A multiport memory emulator that concurrently processes memory commands using a two-level architecture, translating logical addresses into physical addresses through a lookup table to enable simultaneous read and write operations without the need for additional ports, thereby maintaining performance and power efficiency similar to single-port memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If space-multiplexing multiport memories are implemented using larger bitcells, then the memory can support multiple ports, but the layout area increases exponentially
Solution Approach 1:
The patent uses a single-port memory device and creates multiple logical ports through address translation and time-multiplexing. Instead of physically replicating multiple ports, the system copies the functionality of multiple ports through software/firmware address translation layers that map logical multiport addresses to the single physical port, eliminating the need for larger multiport bitcells
Solution Approach 2:
The single-port memory device is made universal by implementing an address translation mechanism that allows it to serve multiple logical ports. The address translation logic enables the same physical memory resource to be accessed by multiple logical addresses simultaneously through time-multiplexing, making one device perform the function of multiple port memory
2Area of stationary object
If time-multiplexing is used to implement multiport memories, then the layout area is reduced, but the frequency of operation decreases and cycle latency increases
Solution Approach 1:
The patent performs address translation in advance before memory access operations. The address translation logic pre-computes the mapping between logical multiport addresses and physical single-port addresses, allowing the memory device to operate at its native high frequency without waiting for address resolution during access cycles
Solution Approach 2:
The patent introduces an address translation layer as an intermediary between the logical multiport interface and the physical single-port memory. This mediator handles the address mapping transparently, allowing the memory device to maintain its native high-speed operation while providing multiport functionality through the translation layer
3Productivity
If multiple-input and multiple-output memories are implemented, then concurrent read and write operations are supported, but the area and power consumption double
Solution Approach 1:
The patent uses periodic time-multiplexing to alternate between read and write operations on the single-port memory device. By carefully managing the timing and prioritization of read/write requests through address translation, the system provides the appearance of concurrent read/write capability while using a single physical port that operates at high frequency
Data Source
AI summary
A multiport memory emulator receives first and a second memory commands for concurrent processing of memory commands in one operation clock cycle. Data operands are stored in a memory array of bitcells that is arranged as rows and memory banks. An auxiliary memory bank provides a bitcell for physically storing an additional word for each row. The bank address portion of each of the first and second memory commands is respectively translated into a first and second physical bank address. The second physical bank address is assigned a bank address of a bank that is currently unused in response to a determination that the bank address portions are equal and the bank associated with the first bank address is designated as a currently unused bank for subsequently received memory commands in response to the determination that the bank address portions are equal. Simultaneous read and write operations are possible.