Multiprocessor Shared Memory Power Saving Control
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Solution Overview
Problem
In multiprocessor/multicore systems, safely transitioning shared memory between power saving and normal modes is challenging due to unauthorized access and data inconsistency risks, necessitating effective power saving mode control to manage accesses to shared memory.
Innovation Solution
A multiprocessor system architecture with a main system and a subsystem, featuring a shared memory and a secondary memory, includes a stop unit to halt accesses and a switching unit to redirect access destinations, ensuring safe transitions between power saving and normal modes by using SRAM and SDRAM effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the shared memory is set in a power saving state to reduce consumption power, then power consumption is reduced, but unauthorized access and data inconsistency occur if processor accesses are not properly stopped
Solution Approach 1:
The stop unit stops accesses from all processors to the shared memory before the shared memory is set in the power saving state. This preliminary action prevents unauthorized access and data inconsistency that would occur if the memory entered power saving mode while processors were still accessing it.
Solution Approach 2:
The stop unit acts as an intermediary control mechanism between the processors and the shared memory. It mediates the transition to power saving mode by ensuring all processor accesses are halted before the memory enters the low-power state, thus protecting data consistency while enabling power savings.
2Ease of operation
If the shared memory is set in a normal state to allow processor accesses, then system functionality is maintained, but consumption power increases
Solution Approach 1:
The system dynamically transitions the shared memory between normal state and power saving state based on operational requirements. The control unit monitors system state and adjusts the memory power mode accordingly, allowing the memory to be in normal state when processors need access and in power saving state when not needed, thus balancing functionality and power consumption.
Solution Approach 2:
The system periodically transitions the shared memory between operational states. The control unit manages periodic checks to determine whether processors need access to the shared memory, switching to power saving mode when not needed and returning to normal mode when needed, creating a rhythmic pattern of power consumption that reduces overall energy usage while maintaining functionality.
3Loss of energy
If a power saving mode program is executed using only SRAM to reduce power consumption, then SDRAM can be set in power saving state, but access speed may be reduced compared to using SDRAM
Solution Approach 1:
The system uses different memory types for different purposes: SRAM is used specifically for power saving mode programs where low power consumption is the priority, while SDRAM is used for normal mode operations where high speed is required. This local quality assignment optimizes performance for each operational context.
Solution Approach 2:
The system changes the operational parameters by switching between different memory types based on the power mode. When in power saving mode, the system configures to use SRAM with its characteristics (lower speed, lower power). When in normal mode, it switches to SDRAM with its characteristics (higher speed, higher power), thus adapting memory parameters to match operational requirements.
Data Source
AI summary
A multiprocessor system configured to share processes by a main system having a first processor and a subsystem having a second processor, comprises a first shared memory configured to receive accesses from the main system and the subsystem, a second memory configured to receive access from the subsystem at a power saving mode, a stop unit configured to stop accesses from the main system and the subsystem to the first shared memory when the subsystem enters the power saving mode, and a switching unit configured to switch an access destination of the subsystem from the first shared memory to the second memory when the subsystem enters the power saving mode.