Multi-Sheet Transistor Structure for Short-Channel Control
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Solution Overview
Problem
Current semiconductor devices face challenges in improving performance and reliability, particularly in scaling techniques for multi-gate transistors, where the short channel effect (SCE) and current control are not adequately addressed.
Innovation Solution
The semiconductor device incorporates a specific structure with a lower pattern and sheet patterns on a substrate, featuring gate structures, spacers, and source/drain patterns with a semiconductor liner film and filling film, including silicon-germanium, to enhance current control and suppress the short channel effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistor scaling is performed to increase device density, then device density is improved, but short channel effect becomes more severe
Solution Approach 1:
The patent transitions from planar 2D channel structure to three-dimensional multi-gate structure (FinFET, nanowire, or multi-bridge channel configurations). By adding vertical dimension and creating multiple gates that wrap around the channel, the effective gate control length increases while physical gate length can be scaled down, thereby maintaining SCE suppression at higher device densities
Solution Approach 2:
The channel region is divided into multiple segments with separate gates controlling each segment (multi-gate configuration). This segmentation allows independent optimization of each gate-channel interface, improving overall gate control efficiency and reducing the impact of short channel effects while enabling higher device density through compact arrangement
2Reliability
If gate length is increased to suppress short channel effect, then short channel effect suppression is improved, but current control capability deteriorates
Solution Approach 1:
By moving to three-dimensional multi-gate structures where gates wrap around the channel from multiple directions, the effective gate control perimeter increases without requiring longer gate length. This provides stronger electrostatic control over the channel potential, suppressing SCE while maintaining excellent current modulation capability through enhanced gate-to-channel coupling
Solution Approach 2:
The patent employs composite material structures including high-k dielectric gate insulators combined with metal gates, and multi-layer semiconductor channels with different compositions (e.g., Si/SiGe). These composite structures enable independent optimization of gate control strength and current flow characteristics, achieving both SCE suppression and high current control capability
3Ease of manufacture
If conventional source and drain structures are used in multi-gate transistors, then manufacturing simplicity is maintained, but performance and reliability are insufficient
Solution Approach 1:
The source and drain structures are nested within recesses formed in the substrate, with selective epitaxial growth creating multi-layer semiconductor structures (e.g., Si/SiGe/Si) that are integrated into the three-dimensional channel architecture. This nested configuration enables complex functionality while maintaining compatibility with standard CMOS manufacturing processes through sequential deposition and etching steps
Data Source
AI summary
A semiconductor device includes an active pattern including a lower pattern extending a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction, the plurality of sheet patterns including an uppermost sheet pattern, a plurality of gate structures disposed to be spaced apart from each other in the first direction on the active pattern and including gate electrodes extending in a third direction and gate spacers on sidewalls of the gate electrodes and a source/drain pattern disposed between the gate structures adjacent to each other and including a semiconductor liner film and a semiconductor filling film on the semiconductor liner film, wherein the semiconductor liner film covers a portion of an upper surface of an uppermost sheet pattern.