Multisided Wafer Test Head Architecture for Dual-Sided Testing

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Solution Overview

Problem

Traditional automated test equipment (ATE) for wafers can only test one wafer at a time, limiting throughput and increasing costs due to the need for multiple test sites and increased manufacturing facility space, especially in high-volume integrated circuit production.

Innovation Solution

A multisided wafer test head architecture that allows simultaneous or interleaved testing of multiple wafers using printed circuit boards (PCBs) with connectors on both sides, enabling electrical connections to both the front and back panels, thereby doubling the testing capacity and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional single-sided wafer test head architecture is used, then the device complexity is low and ease of manufacture is good, but the productivity is limited to one wafer at a time

Engineering Contradiction:
Improvewafer testing throughputVSAvoidtest head architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent transitions from a single-sided test head to a dual-sided test head architecture, utilizing both the front and back sides of the test head for wafer testing. This dimensional change allows two wafers to be tested simultaneously on opposite sides of the same test head, effectively doubling the testing throughput without proportionally increasing device complexity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The test head is designed to perform the same wafer testing function on both its front and back sides. Each side contains complete testing capabilities including probe cards, positioning mechanisms, and electrical connections, allowing the single test head to serve multiple testing purposes simultaneously

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If multiple ATE units are purchased to increase testing capacity, then the productivity increases, but the manufacturing facility space and costs increase

Engineering Contradiction:
Improvetesting capacityVSAvoidmanufacturing facility space
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent combines two testing stations into one dual-sided test head unit. By integrating front-side and back-side testing capabilities into a single compact test head that mounts on one ATE unit, the system achieves the equivalent throughput of two separate ATE units while occupying only the space of one unit in the manufacturing facility

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If traditional single-sided test head is used, then the ease of operation is simple, but the productivity is limited

Engineering Contradiction:
Improvedevice under test throughputVSAvoidtesting operation complexity
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The dual-sided test head is pre-configured with both front and back probe cards, positioning mechanisms, and electrical connections ready for simultaneous operation. This preliminary preparation allows operators to load wafers on both sides and initiate testing without complex setup procedures, maintaining ease of operation while doubling throughput

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7378860B2Wafer test head architecture and method of use
Publication Date: 2008.05.27 ADVANTEST CORP
  • US7378860B2 patent drawing
  • US7378860B2 patent drawing
  • US7378860B2 patent drawing

AI summary

A wafer test head and ATE for testing semiconductor wafers. The wafer test head having a plurality of sides that can each be used to test a different semiconductor wafer. The architecture of the wafer test head enables electrical connections to probe card located on two different sides of the wafer test head. Multiple silicon wafers can be tested for proper functionality at the same time or in an interleaved fashion via a single multi-sided wafer test head. The internal architecture of an exemplary wafer test head allows printed circuit cards to be able to electrically connected to multiple wafer test locations on a single wafer test head.