Multi-Stack Diffusion Break Layout for Transistor Isolation Density
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Solution Overview
Problem
In semiconductor device design, achieving high device density while maintaining performance is challenging, particularly in isolating transistors in dense arrays, where existing diffusion break structures either compromise on isolation or density.
Innovation Solution
The implementation of a multi-stack semiconductor device with selectively formed diffusion break structures on both lower and upper stacks, utilizing void spaces between gate structures to isolate adjacent transistors, allowing for efficient stress control and density optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a double diffusion break structure (DDB) is used to isolate adjacent transistors, then isolation performance is improved, but device density decreases due to the larger area occupied
Solution Approach 1:
The diffusion break structure is divided into two separate structures positioned at different vertical levels (first and second vertical positions). This segmentation allows each diffusion break to occupy a smaller horizontal area while collectively providing the isolation function, thereby improving device density without sacrificing isolation performance.
Solution Approach 2:
The patent transitions from a single-plane diffusion break structure to a multi-vertical-level structure. By utilizing the vertical dimension to position diffusion breaks at different heights, the design reduces the horizontal footprint of each diffusion break while maintaining effective isolation between adjacent transistors through the combined effect of multiple vertically-staggered structures.
2Quantity of substance
If a single diffusion break structure (SDB) is used to increase device density, then device density is improved, but isolation performance deteriorates
Solution Approach 1:
The patent combines multiple diffusion break structures at different vertical positions to achieve the isolation performance of a full DDB. By merging the isolation effects of the first and second diffusion breaks positioned at different vertical levels, the design attains superior isolation while maintaining the area efficiency of SDB-like compact structures.
Data Source
AI summary
A multi-stack semiconductor device includes: a plurality of lower transistor structures arranged on a lower stack and including a plurality of lower fin structures surrounded by a plurality of lower gate structures, respectively; a plurality of upper transistor structures arranged on an upper stack and including a plurality of upper fin structures surrounded by a plurality of upper gate structures, respectively; and at least one of a lower diffusion break structure on the lower stack and a upper diffusion break structure on the upper stack, wherein the lower diffusion break structure is formed between two adjacent lower gate structures, and isolates two lower transistor structures respectively including the two adjacent lower gate structures from each other, and the upper diffusion break structure is formed between two adjacent upper gate structures, and isolates two upper transistor structures respectively including the two adjacent upper gate structures from each other.