Multi-Stage Charge Pump Circuit for High Voltage Without Capacitor Stress
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in generating output voltages higher than the power supply voltage without additional circuitry, leading to issues like voltage drop in bit line voltages and the need for boosting voltages in components like sense amplifiers and data buffers.
Innovation Solution
A multi-stage charge pump circuit is designed with a first and second pumping stage, each comprising pumping capacitors and transistors, and transfer stages that operate in complementary modes during a single clock cycle to generate an output voltage multiple times the input voltage, while controlling capacitor voltages within the input voltage range to prevent degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a conventional charge pump circuit is used to generate boosting voltage, then the output voltage can be higher than input voltage, but the capacitor voltage exceeds the input voltage causing degradation and reliability issues
Solution Approach 1:
The charge pump circuit is divided into multiple pumping stages (first pumping stage, second pumping stage, etc.), where each stage contributes a portion of the voltage multiplication. This segmentation allows the total output voltage to be achieved through cumulative addition of smaller voltage increments from each stage, ensuring that no single capacitor experiences voltage stress exceeding the input voltage level.
Solution Approach 2:
The circuit employs dynamic switching of capacitors between different operational modes (pumping mode and precharge mode) based on clock signal phases. This dynamic reconfiguration ensures that capacitors are always operated within safe voltage limits while collectively achieving the desired high output voltage through coordinated operation of multiple stages.
2Power
If multiple pumping stages are added to increase output voltage, then the boosting capability is improved, but the circuit area and complexity increase
Solution Approach 1:
Each pumping stage is designed as a universal module that can be replicated and configured in different numbers to achieve various output voltage levels. The same basic circuit topology and capacitor structures are reused across stages, reducing design complexity and allowing flexible voltage scaling without proportionally increasing overall circuit complexity.
Solution Approach 2:
Adjacent pumping stages share common nodes and capacitors, and the transfer stages are integrated to efficiently couple between stages. This merging approach reduces the total number of discrete components compared to fully independent stage designs, thereby reducing overall circuit area and complexity while maintaining the multi-stage voltage multiplication capability.
3Power
If conventional multi-stage boosting circuit is used, then high output voltage is achieved, but the circuit occupies larger area
Solution Approach 1:
The circuit employs nested capacitor configurations where capacitors in adjacent stages share physical space and electrical nodes. The transfer stages are integrated within the same physical layout as the pumping stages, creating a compact nested structure that reduces overall circuit footprint compared to conventional multi-stage designs where each stage would be fully discrete and separated.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit efficiently generates high output voltages with reduced capacitor degradation, smaller area requirements, and improved reliability by minimizing pumping loss and transistor count, enabling efficient operation from low input voltages.
Implementation Method 1
a first pumping capacitor C1 including a first end to which a clock signal CLK is applied and a second end connected with a first node N1, and a second pumping capacitor C2 including a first end to which an inverse clock signal CLKB is applied and a second end connected with a second node N2
Data Source
AI summary
A charge pump circuit of a semiconductor memory device, which may include a first pumping stage that includes a first pumping capacitor and a second pumping capacitor, a first transfer stage that transfers a voltage of the first pumping capacitor when a clock signal is at a high level or transfers a voltage of the second pumping capacitor when a inverse clock signal is at the high level, a second pumping stage that includes a third pumping capacitor and a fourth pumping capacitor, and a second transfer stage that transfers a voltage of the third pumping capacitor when the clock signal is at the high level or transfers a voltage of the fourth pumping capacitor when the inverse clock signal is at the high level. The second transfer stage may output multiple times of the input voltage.