Multi-Stage DFE Latch Architecture for High-Speed Receiver Gain
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Solution Overview
Problem
High-speed data receivers face challenges in timely computation and distribution of Decision Feedback Equalization (DFE) corrections across multiple parallel processing phases, leading to reduced detector amplification and gain due to the complexity of combining many DFE correction terms and the difficulty in achieving timely propagation of corrections at high data rates.
Innovation Solution
The method involves pre-charging sets of nodes to generate differential output signals, combining data voltage signals with aggregate DFE correction signals, and using speculative DFE to apply corrections without significant impact on detector gain, by partitioning summations among multiple circuits and utilizing multi-input summation latches to efficiently compute and distribute DFE corrections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple parallel processing phases are used to pipeline detection, then detector amplification and gain are improved, but computation and distribution of DFE corrections becomes more complex and time-consuming
Solution Approach 1:
The patent divides the DFE correction computation into multiple independent stages, each corresponding to a parallel processing phase. Each stage computes corrections for a specific number of previous unit intervals (e.g., first stage handles 2-3 intervals, second stage handles 4-5 intervals). This segmentation allows each stage to operate independently with reduced computational complexity while maintaining the benefits of multiple parallel processing phases.
Solution Approach 2:
The patent introduces a temporal dimension to the DFE correction computation by organizing corrections into multiple stages that process different time intervals sequentially. Instead of computing all corrections simultaneously in a single complex operation, the system distributes corrections across multiple time stages, each handling a specific temporal range of previous data values.
2Measurement precision
If DFE corrections are combined across multiple parallel processing phases, then detection accuracy is improved, but detector gain is reduced due to the complexity of combining corrections
Solution Approach 1:
The patent segments the DFE correction combination process into multiple independent stages. Each stage combines corrections for a specific subset of previous unit intervals rather than combining all corrections in a single operation. This segmentation prevents the detector gain reduction that would result from combining all corrections simultaneously, while still achieving improved detection accuracy through the cumulative effect of multiple stages.
3Speed
If timely computation of DFE corrections is achieved at high data rates, then data communication speed is improved, but circuit delays and processing elements increase
Solution Approach 1:
The patent segments the DFE correction computation into multiple stages, each handling a specific number of previous unit intervals. This segmentation reduces the computational burden on any single circuit element, allowing high-speed operation without requiring excessively complex or slow processing elements. Each stage can be implemented with simpler, faster circuitry.
Solution Approach 2:
The patent performs DFE correction computations in advance for future unit intervals and stores them in buffers. This preliminary computation allows the receiver to operate at high data rates without waiting for real-time correction calculations, as corrections are pre-computed and ready for application when needed.
Data Source
AI summary
Pre-charging two or more sets of nodes to set a differential output of a multi-input summation latch connected to the two or more sets of nodes in a pre-charged state, the two or more sets of nodes comprising a set of data signal nodes and a set of DFE correction nodes, in response to a sampling clock, generating a differential data voltage and an aggregate differential DFE correction signal, and generating a data decision by driving the differential output of the multi-input summation latch into one of two possible output states according to a summation of the differential data voltage signal and the aggregate differential DFE correction signal and subsequently holding the data decision by holding the differential output of the multi-input summation latch in a latched state for a duration determined by the sampling clock.