Multithread Processor Dynamic Throttling Bandwidth

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Solution Overview

Problem

As processor functionality increases, so does power consumption, which is a concern in applications like mobile computing where reduced power consumption is desired to extend battery life, and there is a need for dynamic throttling to adjust execution bandwidth and power usage based on workload.

Innovation Solution

A multithreaded processor with dynamic thread-based throttling capabilities that aggregates execution bandwidth requests across threads and adjusts clock frequency and voltage to either increase execution bandwidth or reduce power consumption, allowing for real-time scaling based on workload demands.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If processor functionality and features are increased, then processing capability is improved, but power consumption increases

Engineering Contradiction:
Improveprocessing capabilityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The processor implements dynamic throttling by adjusting clock frequency and voltage based on aggregated execution bandwidth requests from multiple threads. The regulator dynamically scales operating characteristics in response to workload changes, allowing the processor to adapt its power consumption and performance levels according to actual execution needs rather than operating at fixed high-performance settings.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes physical operating parameters (clock frequency and voltage) based on aggregated bandwidth allocation requests. By monitoring and aggregating execution bandwidth requests across threads, the processor modifies its operating parameters to match actual workload demands, thereby reducing power consumption when full processing capability is not required.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If clock frequency and voltage are scaled up, then execution bandwidth is increased, but power consumption increases

Engineering Contradiction:
Improveexecution bandwidthVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The regulator dynamically adjusts clock frequency and voltage based on real-time aggregation of execution bandwidth requests from instruction execution threads. This dynamic adjustment allows the processor to scale performance up or down according to actual workload requirements, avoiding unnecessary power consumption when high execution bandwidth is not needed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system implements feedback by continuously monitoring execution bandwidth allocation requests from threads, aggregating these requests, and using the aggregated information to adjust clock frequency and voltage. This closed-loop feedback mechanism ensures that power consumption is optimized based on actual execution needs rather than operating at fixed high-performance levels.

Inventive Principle:
Principle #23Feedback

3Use of energy by moving object

If dynamic throttling is implemented, then power consumption is reduced, but system complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidsystem complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The scheduler performs multiple functions: it manages thread execution scheduling and simultaneously aggregates execution bandwidth requests to control processor throttling. This multi-functionality reduces the need for separate dedicated hardware components for bandwidth aggregation and throttling control, thereby limiting the increase in system complexity while still achieving dynamic power management.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7886131B1Multithread processor with thread based throttling
Publication Date: 2011.02.08 MARVELL ASIA PTE LTD
  • US7886131B1 patent drawing
  • US7886131B1 patent drawing
  • US7886131B1 patent drawing

AI summary

A multithreaded processor with dynamic thread based throttling, more specifically, based at least in part on the aggregated execution bandwidth requests of the threads, is disclosed herein. In various embodiments, the multithreaded processor may throttle by scaling clock frequency and/or voltage provided to the processor, based at least in part on the aggregated execution bandwidth requests of the threads. The aggregation and scaling may be performed when a bandwidth allocation request of an instruction execution thread is modified or when a computation intensive instruction execution thread is activated or re-activated. Other embodiments and/or features may also be described and claimed.