Multi-Threaded MRAM Cell Architecture for Instant-On Memory
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Solution Overview
Problem
Existing memory cells in portable devices face challenges in increasing computing capabilities while minimizing size and power usage, as adding multiple ports to SRAM cells increases circuit complexity and power consumption.
Innovation Solution
A multi-ported and multi-threaded magnetoresistive random access memory (MRAM) device with multiple non-volatile resistive memory elements, allowing for simultaneous data storage and retrieval across multiple threads without the need for additional circuitry, enabling instant-on architecture and reduced start-up times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple ports are added to SRAM cells to support simultaneous multi-threading, then memory bandwidth and computing capability are improved, but device complexity and power consumption increase
Solution Approach 1:
The patent combines multiple memory cells into a single integrated structure that supports multiple ports and multiple threads. Instead of implementing separate memory cells for each port/thread combination, the invention merges them into a unified cell structure that handles multiple access ports and thread contexts simultaneously, thereby reducing overall device complexity while maintaining high memory bandwidth.
Solution Approach 2:
The memory cell is designed with multi-functionality to serve multiple purposes: it supports multiple access ports, multiple thread contexts, and both volatile and non-volatile storage functions within a single cell structure. This universal design allows the same cell to handle various operations (read, write, hold, restore) across different ports and threads without requiring dedicated specialized cells for each function.
2Productivity
If multiple ports are added to SRAM cells to support simultaneous multi-threading, then memory bandwidth is improved, but power consumption increases
Solution Approach 1:
The patent changes the fundamental parameter of memory cell type from traditional volatile SRAM to a hybrid structure incorporating non-volatile resistive memory elements. This parameter change enables the cell to maintain data without continuous power during idle periods between thread executions, significantly reducing power consumption while still supporting high bandwidth operations when multiple ports are actively accessing data.
Solution Approach 2:
The memory cell operates in periodic cycles where data is actively accessed during thread execution and then held in a low-power state between accesses. The non-volatile portion maintains data integrity during these idle periods, allowing the cell to consume power only during active read/write operations rather than continuously, thus reducing overall power consumption while maintaining high bandwidth during active periods.
3Loss of time
If non-volatile memory elements are used to support instant-on architecture, then start-up time is reduced and data integrity is improved, but device complexity increases
Solution Approach 1:
The memory cell is segmented into distinct volatile and non-volatile portions, each serving specific functions. The non-volatile segment (resistive memory element) is responsible for maintaining data during power-off periods and enabling instant-on functionality, while the volatile segment handles active data manipulation. This segmentation allows the system to achieve fast start-up without requiring the entire memory structure to be redesigned for non-volatile operation, thus limiting the increase in device complexity to only the necessary non-volatile components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a compact and power-efficient memory solution that supports simultaneous multi-threading, reducing start-up times and maintaining data integrity even when powered off, by utilizing resistive memory elements that store state information instantly accessible upon power-on.
Implementation Method 1
A multi-ported and multi-threaded magnetoresistive random access memory (MRAM) device... each of the memory cells comprises a first multi-port non-volatile memory including a first resistive memory element and a second multi-port non-volatile memory including a second resistive memory element
Implementation Method 2
A multi-ported and multi-threaded magnetoresistive random access memory (MRAM) device...
Data Source
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AI summary
A system comprising a processor processing two threads, a memory device in communication with the processor, the memory device receiving an input address signal and comprising a plurality of groups of memory cells, each group of memory cells including two non-volatile memory cells having a same input address, each memory cell including a resistive memory element and associated with a corresponding thread.