Multi-Value Memory Cell Array Decoding for Faster Program-Erase-Read
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Solution Overview
Problem
Existing technologies face challenges in efficiently programming, erasing, and reading multi-value non-volatile memory cells in an array format, necessitating improved array designs and decoders for efficient operation.
Innovation Solution
The development of an array of multi-value non-volatile memory cells with specific decoder configurations, including bit line, row, erase gate, control gate, and word line decoders, that facilitate efficient programming, erasing, and reading operations by applying precise voltage configurations to the terminals of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in an array format, then storage capacity is improved, but programming, erasing, and reading efficiency deteriorates
Solution Approach 1:
The patent divides the array of memory cells into multiple groups, where each group shares common control terminals (erase gate terminals and control gate terminals). This segmentation allows independent control and operation of specific cell groups, enabling efficient programming, erasing, and reading of selected cells without affecting the entire array, thus maintaining high storage capacity while improving operational efficiency.
Solution Approach 2:
The patent implements multi-functional decoders that can perform multiple operations (programming, erasing, reading) through a single decoder structure. The decoders are designed to selectively activate different memory cell groups based on decoded signals, allowing one decoder system to handle multiple functions and operations on multiple cell groups simultaneously, thereby improving productivity without sacrificing storage capacity.
2Productivity
If decoder configurations are added to improve operation efficiency, then programming, erasing, and reading efficiency is improved, but device complexity increases
Solution Approach 1:
The patent merges the functions of multiple decoders into a single integrated decoder structure that can handle programming, erasing, and reading operations. By combining these functions into one decoder system that selectively controls different memory cell groups, the patent reduces the number of separate decoder components needed, thereby lowering device complexity while maintaining improved operational efficiency.
Solution Approach 2:
The decoder is designed as a universal component that performs multiple functions (programming, erasing, reading) through different signal configurations. This multi-functional design eliminates the need for separate dedicated decoders for each operation, reducing overall device complexity while achieving high productivity through a single versatile decoder system.
Data Source
AI summary
In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a first bit line terminal, a first erase gate terminal, a first control gate terminal, a first floating gate, a word line, a second floating gate, a second control gate terminal, a second erase gate terminal, and a second bit line terminal, wherein the first floating gate can store a first digital or analog value and the second floating gate can store a second digital or analog value; and a bit line decoder for a column to selectively provide a first voltage to the first bit line terminals of non-volatile memory cells in the column and a second voltage to the second bit line terminals of the non-volatile memory cells in the column.