Glitch-Free Multiplexer Timing Using Delayed Ready Sampling
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Solution Overview
Problem
Conventional sequential circuitry experiences power dissipation issues due to glitches in signals, which cause unnecessary charging and discharging of nodes, leading to increased power consumption and inefficiency.
Innovation Solution
A storage element is inserted to sample the signal after it has stabilized, using a 'ready' signal with a delay matching the circuitry's delay, ensuring the output signal changes only once, thereby reducing power dissipation by preventing glitch propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional sequential circuitry uses combinational logic with synchronous registers, then the circuit can process data, but glitches occur in the output signal causing multiple changes before settling to final state
Solution Approach 1:
A storage element is introduced as an intermediary between the combinational logic and the output to capture the signal after it has stabilized. The storage element is enabled by a ready signal that is delayed to match the combinational logic delay, ensuring the signal is sampled only after glitch-free stabilization, thus eliminating output glitches without fundamentally changing the combinational logic structure
2Use of energy by moving object
If the output signal changes multiple times before settling to final state, then the multiplexer can respond to changing inputs, but additional combinational logic charges and discharges nodes dissipating power
Solution Approach 1:
The ready signal is generated in advance with a delay that matches the combinational logic delay, enabling the storage element to be activated at the precise moment when the signal has stabilized. This preliminary timing arrangement ensures that the storage element captures the glitch-free signal state before any subsequent changes occur, preventing unnecessary node charging and discharging in receiving logic
Data Source
AI summary
When a signal glitches, logic receiving the signal may change in response, thereby charging and/or discharging nodes within the logic and dissipating power. Providing a glitch-free signal may reduce the number of times the nodes are charged and/or discharged, thereby reducing the power dissipation. A technique for eliminating glitches in a signal is to insert a storage element that samples the signal after it is done changing to produce a glitch-free output signal. The storage element is enabled by a “ready” signal having a delay that matches the delay of circuitry generating the signal. The technique prevents the output signal from changing until the final value of the signal is achieved. The output signal changes only once, typically reducing the number of times nodes in the logic receiving the signal are charged and/or discharged so that power dissipation is also reduced.