3D NAND Memory Array Layout With Shared Word Lines
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Solution Overview
Problem
The challenge of increasing chip area in semiconductor memory devices, particularly in three-dimensional stacked NAND flash memory, has not been adequately addressed by existing technologies.
Innovation Solution
A semiconductor memory device design where the first and second memory cell arrays are stacked with shared word lines but unconnected select gate lines, allowing for efficient use of space by independently connecting select gate lines of each array to separate decoders, thereby optimizing the layout and reducing the overall chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory cell arrays are stacked with shared word lines and select gate lines, then device integration is improved, but chip area increases
Solution Approach 1:
The patent divides the select gate line control into independent segments for each memory cell array. Each array has its own select gate lines connected to separate decoders, allowing independent control and reducing the need for extensive wiring between stacked arrays, thereby preventing chip area expansion while maintaining high integration.
Solution Approach 2:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked architecture. Multiple memory cell arrays are vertically stacked with word lines shared across arrays, while select gate lines are independently routed to each array's decoder in the vertical dimension, enabling high integration without proportional increases in chip footprint.
2Adaptability or versatility
If select gate lines of stacked memory cell arrays are independently connected to separate decoders, then control flexibility is improved, but device complexity increases
Solution Approach 1:
The control system is segmented into multiple independent decoder units, each dedicated to controlling select gate lines of a specific memory cell array. This segmentation provides control flexibility for independent array operations while distributing complexity across modular units rather than concentrating it in a single complex decoder.
Solution Approach 2:
Each decoder unit serves as a universal control component that can independently manage the select gate lines of its associated memory cell array. This multi-functional approach allows the same decoder architecture to be replicated across multiple arrays, providing control flexibility while using standardized, manageable complexity units.
Data Source
AI summary
A semiconductor memory device includes first and second memory cell arrays. The first array includes a first semiconductor portion, extending in a first direction, on which a first memory cell and a first select transistor are formed, a first word line connected to the first cell, a first select gate line connected to the first transistor, and a first bit line connected to the first semiconductor portion. The second array includes a second semiconductor portion, extending along the first direction, on which a second memory cell and a second select transistor are formed, a second word line connected to the second cell, a second select gate line connected to the second transistor, and a second bit line connected to the second semiconductor portion. The first and second word lines are electrically connected, but the first and second select gate lines are not electrically connected.