Configurable Bit Line Isolation in NAND Memory
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Solution Overview
Problem
Current memory systems face challenges in efficiently programming and reading data due to noise interference from unselected bit lines, which can lead to inaccurate readings and longer processing times.
Innovation Solution
The implementation of configurable isolation of bit lines using dummy memory cells with different threshold voltages, allowing for selective electrical coupling or isolation of NAND strings, thereby reducing noise and enabling simultaneous pre-charging of bit lines before address receipt, and precise discharge of selected bit lines during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If all bit lines are pre-charged simultaneously before address receipt, then read speed is improved, but noise interference from unselected bit lines increases causing reading inaccuracies
Solution Approach 1:
The patent segments bit lines into two distinct groups: selected bit lines that are pre-charged and connected to memory cells, and unselected bit lines that are isolated from memory cells. This segmentation is achieved through configurable isolation mechanisms that prevent unselected bit lines from discharging, thereby eliminating noise interference while maintaining fast read speeds for selected bit lines.
Solution Approach 2:
The patent introduces an intermediary isolation mechanism between unselected bit lines and memory cells. This intermediary structure prevents direct electrical connection during pre-charge operations, blocking the propagation of discharge signals from unselected bit lines to memory cells, thus eliminating noise while preserving the benefits of simultaneous pre-charging.
2Productivity
If unselected bit lines are electrically connected to memory cells during pre-charge, then pre-charging efficiency is improved, but noise interference increases causing inaccurate readings
Solution Approach 1:
The patent implements dynamic electrical connection control where the connection state between bit lines and memory cells changes based on selection status. During pre-charge operations, unselected bit lines are dynamically isolated from memory cells while selected bit lines maintain connection. This dynamic reconfiguration enables efficient pre-charging of selected lines without the harmful noise effects from unselected lines.
Solution Approach 2:
The patent segments the electrical connection topology into connected and isolated portions. Unselected bit lines are separated from memory cells through isolation structures, while selected bit lines maintain direct connection. This segmentation allows unselected bit lines to be pre-charged efficiently without their discharge affecting memory cell readings, thus eliminating noise interference while preserving pre-charging efficiency.
3Measurement precision
If bit lines are isolated from memory cells, then noise interference is reduced improving reading accuracy, but read time increases due to sequential operations
Solution Approach 1:
The patent performs preliminary isolation of unselected bit lines from memory cells before the actual read operation begins. By pre-configuring the electrical connection state based on address decoding, the system eliminates noise interference in advance, allowing subsequent read operations to proceed quickly without requiring additional time for noise mitigation or sequential processing.
Solution Approach 2:
The patent implements dynamic reconfiguration of bit line connections that occurs rapidly during the address decode phase. Selected bit lines are dynamically connected to memory cells while unselected bit lines are dynamically isolated. This dynamic switching happens before the read operation, enabling both high reading accuracy through isolation and fast read times through parallel pre-charging of selected lines.
Data Source
AI summary
An apparatus is provided that includes a plurality of NAND strings having a common set of word lines. Each NAND string includes data memory cells for data storage and dummy memory cells connected in series with the data memory cells. A first group of NAND strings includes dummy memory cells with a first pattern of threshold voltages and a second group of NAND strings includes dummy memory cells with a second pattern of threshold voltages for separate isolation of data memory cells of the first and second groups of NAND strings from corresponding bit lines.