NAND Flash Page Buffer Throughput via Bit Line Select Gates
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Solution Overview
Problem
The limitations of traditional NAND flash memory architectures, where the large size of page buffers restricts the number of bit lines that can be programmed or read simultaneously, leading to reduced read/write throughput due to the occupation of a significant portion of the die size.
Innovation Solution
The introduction of bit line select gates that allow page buffers to connect to multiple bit lines, enabling simultaneous programming and reading of multiple bit lines, along with additional pass gates and data registers to enhance operation, and novel programming and reading operations to increase performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of page buffers is increased to increase data read/write throughput, then the read/write performance is improved, but the die size occupied by page buffers increases significantly
Solution Approach 1:
The patent divides the memory system into multiple independent memory blocks, each with its own dedicated page buffer. This segmentation allows each page buffer to serve multiple bit lines within its block through the bit line select gate mechanism, effectively increasing the utilization rate of each page buffer and reducing the total number of page buffers needed across the entire die.
Solution Approach 2:
Each page buffer is designed to be multi-functional by enabling it to connect to and serve multiple bit lines (e.g., 8-16 bit lines) through bit line select gates. This universality allows a single page buffer to perform the function of what would traditionally require multiple dedicated page buffers, thereby reducing the overall page buffer area while maintaining or increasing throughput.
2Area of stationary object
If the number of page buffers is limited to reduce die size, then the area occupation is reduced, but the data read/write throughput is restricted
Solution Approach 1:
The patent introduces a new dimensional approach by adding bit line select gates as an intermediate control layer between page buffers and bit lines. This creates a hierarchical structure where page buffers connect to multiple bit lines through selectable gates, enabling one page buffer to access multiple bit lines in different time slots or simultaneously, thus increasing throughput without proportionally increasing page buffer area.
Solution Approach 2:
Bit line select gates serve as intermediary components that mediate between page buffers and bit lines. These select gates enable a single page buffer to connect to and control multiple bit lines by selectively enabling connections based on which bit line needs to be accessed, thereby amplifying the capacity of limited page buffers without requiring additional page buffer circuits.
3Productivity
If multiple bit lines are connected to a single page buffer to increase throughput, then the data read/write performance is improved, but capacitive coupling between bit lines increases
Solution Approach 1:
The patent applies local quality control by making each bit line connection controllable and selective through individual bit line select gates. Instead of having all bit lines permanently connected to a page buffer (which would cause continuous capacitive coupling), the select gates enable connections only when needed, locally controlling the coupling characteristics for each bit line access operation.
Solution Approach 2:
The bit line select gates are activated periodically or selectively based on which bit line needs to be accessed. This periodic activation means that capacitive coupling is only present during the brief moments when a select gate is enabled, rather than being continuously present. The select gates are turned off between accesses, effectively reducing the time-averaged capacitive coupling between bit lines.
Data Source
AI summary
Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a method is provided for programming a NAND flash memory. The method includes precharging selected bit lines of selected memory cells with a bias voltage level while unselected bit lines maintain the inhibit voltage, applying a verify voltage to a selected word line that is coupled to the selected memory cells, and discharging the selected bit lines that are coupled to on-cells over a first time interval. The method also includes sensing a sensed voltage level on a selected bit line, loading the selected bit line with the inhibit voltage level when the sensed voltage level is above a threshold level and a program voltage when the sensed voltage level is equal to or below the threshold level, and repeating the operations of sensing and loading for each of the selected bit lines.