NAND Bit-Line Erase Control to Prevent Over-Erase

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Solution Overview

Problem

Over-erase of NAND strings in semiconductor memory can lead to data integrity issues, as faster-erasing strings may be over-erased, causing damage and compromising data integrity.

Innovation Solution

A storage system divides bit lines into groups based on the erase status of connected NAND strings, applying different erase voltages to prevent over-erase by ensuring slower erase speeds for certain groups and inhibiting erase for others, using a multi-loop GIDL-based erase procedure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a uniform erase voltage is applied to all bit lines during erase loops, then the erase process is simple to control, but faster-erasing NAND strings will be over-erased causing data integrity issues

Engineering Contradiction:

Improveerase control simplicityVSAvoiddata integrity

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The patent applies different erase voltages to different bit lines based on the erase status of connected NAND strings. Bit lines connected to strings that have not completed erase receive a first erase voltage, while bit lines connected to strings that have completed erase receive a second erase voltage, creating local quality differences in the erase process

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the erase voltage parameter dynamically during the erase process. By switching from a first erase voltage to a second erase voltage based on verify results, the system adapts the erase parameters to prevent over-erase while ensuring complete erasure of all NAND strings

Inventive Principle:

Principle #35Parameter changes

2Reliability

If multiple erase loops are performed to ensure complete erasure of all NAND strings, then data integrity is improved, but the risk of over-erasing faster strings increases

Engineering Contradiction:

Improveerase completenessVSAvoidover-erase damage

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent implements a feedback mechanism where the verify operation monitors the erase status of NAND strings after each erase loop. Based on this feedback, the system determines whether to continue applying the first erase voltage or switch to the second erase voltage, preventing over-erase while ensuring complete erasure

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent uses periodic verify operations between erase loops to check the erase status of NAND strings. This periodic monitoring allows the system to adjust the erase voltage in subsequent loops, ensuring that erasure is complete without causing over-erase damage

Inventive Principle:

Principle #19Periodic action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Prevents over-erase of NAND strings, maintaining data integrity by ensuring uniform erase completion across all strings, thereby reducing damage and improving memory reliability.

Implementation Method 1

Methodology Applied

Scientific EffectGIDL (Gate-Induced Drain Leakage):

Data Source

PatentUS12469569B2Smart erase inhibit

Publication Date: 2025.11.11 SANDISK TECHNOLOGIES LLC

AI summary

Technology to prevent over-erase in NAND memory. Each bit line involved in erase is connected to multiple NAND strings. Erase verify of each NAND string is performed at a final target level and a level that is somewhat higher than the final target level. Bit lines are placed into three groups based on the erase status of the NAND strings connected to the bit line. The erase voltage applied to the bit lines in the next erase loop depends on the group in which the bit line was placed.