3D NAND Bit Line Timing Control for Accurate Vth Programming
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Solution Overview
Problem
Existing bit line bias schemes for programming memory cells in 3D NAND memory devices are complex, leading to increased chip area, reduced Vth shift step size accuracy, and limited regulation of bias voltages, which affects Vth distribution and program endurance.
Innovation Solution
A shift control scheme that controls the effective program duration of program voltages by pre-charging and discharging bit lines to specific bias voltages at different times, allowing for accurate Vth shift step size control without additional charging circuits, thereby reducing chip area and enhancing Vth distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If existing bit line bias schemes are used to program memory cells, then programming can be performed, but the chip area increases due to complexity
Solution Approach 1:
The patent extracts and eliminates the additional charging circuits from the bit line bias scheme. By using the existing peripheral circuit resources to generate and control bit line biases through a shifted timing approach, the design removes unnecessary components that were increasing chip area while maintaining programming functionality.
Solution Approach 2:
The patent makes the existing peripheral circuits perform multiple functions by using them to generate and control bit line biases in addition to their original functions. The same circuit infrastructure is reused for bias generation through timing shifts, eliminating the need for dedicated charging circuits and reducing overall chip area.
2Ease of manufacture
If existing bit line bias schemes are used, then programming can be performed, but manufacturing precision of Vth shift step size decreases
Solution Approach 1:
The patent changes the timing parameter of bit line bias application by introducing a time shift between word line programming voltage and bit line bias. This temporal parameter change enables precise control of the effective programming duration, thereby improving the accuracy of Vth shift step size without requiring additional hardware components.
3Ease of manufacture
If existing bit line bias schemes are used, then programming can be performed, but regulation of bias voltages is limited
Solution Approach 1:
The patent introduces dynamic control of bit line biases through timing shifts. By dynamically adjusting when bit line biases are applied relative to the word line programming voltage, the system achieves flexible and precise regulation of effective programming duration, enhancing adaptability and versatility of bias voltage control without additional charging circuits.
Data Source
AI summary
In certain aspects, a memory device includes a memory cell array and a peripheral circuit. The memory cell array includes memory cells. The peripheral circuit is configured to program at least a subset of the memory cells by applying a first program voltage to a word line coupled to the subset of the memory cells, and verify the programming of the subset of the memory cells to generate a verify result. The subset of the memory cells include first memory cells that are classified into two or more memory-cell groups based on the verify result. The two or more memory-cell groups are coupled to two or more groups of bit lines, respectively. The peripheral circuit is configured to program the first memory cells by applying a second program voltage to the word line and applying a program-enabled bias voltage to the two or more groups of bit lines in two or more different time durations, respectively.