NAND Memory Channel Pre-Charge for Reduced Program Disturb
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Solution Overview
Problem
Existing programming techniques in NAND memory devices suffer from program disturb and inefficient resource utilization due to inadequate pre-charge processes, particularly when programming sub-blocks in reverse order or when certain sub-blocks are already programmed.
Innovation Solution
A two-phase voltage ramp-down process is implemented during the verify operation of a program loop, where the voltages on selected and unprogrammed word lines are reduced in the first phase, followed by a second phase that reduces voltages on all remaining word lines, minimizing program disturb and optimizing channel pre-charge without additional time overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single-phase pre-charge process is used to reduce program disturb, then channel pre-charge is achieved, but programming time increases due to additional overhead
Solution Approach 1:
The patent combines the pre-charge process with the verify operation by performing voltage ramp-down during the verify phase. The verify operation and pre-charge process are merged into a single time window, where the control circuitry ramps down voltages on selected and unprogrammed word lines while simultaneously performing verify reads on other word lines. This eliminates the need for a separate pre-charge phase, thereby reducing programming time while still achieving proper channel pre-charge to minimize program disturb.
Solution Approach 2:
The patent performs the voltage ramp-down action preliminarily during the verify operation, before the actual programming pulse is applied. By initiating the pre-charge process during the verify phase rather than after verify completes, the system prepares the channels in advance for the upcoming programming operation. This preliminary action ensures that channel pre-charge is completed just in time for programming without adding extra time overhead.
2Reliability
If voltages are reduced on all word lines simultaneously to pre-charge channels, then program disturb is minimized, but resource utilization becomes inefficient
Solution Approach 1:
The patent applies different voltage ramp-down strategies to different groups of word lines based on their programming status and selection state. Specifically, the control circuitry ramps down voltages on selected word lines and unprogrammed word lines in the first phase, while maintaining pass voltage on programmed word lines. In the second phase, voltages on remaining word lines are ramped down. This localized approach ensures that pre-charge is applied only where necessary to prevent program disturb, while avoiding unnecessary voltage changes on already-programmed word lines, thereby improving resource utilization.
Solution Approach 2:
The patent segments the word lines into different groups based on their programming status (programmed vs. unprogrammed) and selection state (selected vs. unselected). The pre-charge process is then applied segmentally: first to selected and unprogrammed word lines, then to remaining word lines in a second phase. This segmentation allows the system to optimize resource utilization by applying pre-charge operations only to the necessary subsets of word lines rather than uniformly to all word lines.
3Productivity
If reverse order programming is used to improve programming efficiency, then productivity increases, but program disturb increases due to inadequate channel pre-charge
Solution Approach 1:
The patent performs the voltage ramp-down action preliminarily during the verify operation, before the actual programming pulse is applied. By initiating the pre-charge process during the verify phase rather than after verify completes, the system prepares the channels in advance for the upcoming programming operation. This preliminary action ensures that channel pre-charge is completed just in time for programming without adding extra time overhead.
Data Source
AI summary
The memory device includes a memory block with memory cells arranged in word lines that are divided into sub-blocks. Control circuitry is configured to program each of the word lines of a selected sub-blocks in a plurality of program loops. During at least one program loop, the control circuitry applies a programming pulse to a selected word line. The control circuitry is also configured to simultaneously apply a verify voltage to the selected word line and a pass voltage to unselected word lines. In a first phase of a multi-phase pre-charge process, the control circuitry reduces the voltages applied to the selected word line and at least one unprogrammed word line to a low voltage. In a second phase that follows the first phase, the control circuitry reduces the voltages applied to all word lines that remained at the pass voltage to the low voltage.