NAND Memory Charge-Passage Structure for Retention and Erase Balance
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Solution Overview
Problem
Existing NAND architecture faces challenges in achieving optimal charge-trapping probability and rate while preventing undesired back-migration of charges, which affects both data retention and erase operations.
Innovation Solution
The integration of bandgap-engineered charge-passage structures within the insulative material between charge-storage structures and channel material, featuring a central region with lower charge-trapping probability and rate compared to the first and second regions, helps in addressing these challenges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If charge-storage structures are integrated closer to channel material to improve memory density, then storage capacity increases, but charge leakage and back-migration increase
Solution Approach 1:
The insulative material is segmented into multiple layers with different dielectric properties. The first insulative layer has higher effective oxide thickness to prevent charge leakage, while the second insulative layer has lower effective oxide thickness to enable efficient erase operations. This segmentation allows the system to simultaneously achieve both charge retention and efficient erasure.
Solution Approach 2:
Different regions of the insulative structure are assigned different dielectric qualities. The first insulative layer uses a dielectric material with higher effective oxide thickness specifically at the interface with channel material to prevent charge leakage, while the second layer uses a dielectric material with lower effective oxide thickness to facilitate charge removal during erase operations.
2Speed
If tunnel barrier thickness is reduced to improve programming efficiency, then charge injection speed increases, but charge leakage increases
Solution Approach 1:
The tunnel barrier is segmented into a first tunnel barrier layer and a second tunnel barrier layer with different thicknesses. The first tunnel barrier layer has greater thickness to prevent charge leakage, while the second tunnel barrier layer has lesser thickness to enable efficient charge injection during programming operations.
Solution Approach 2:
Different regions of the tunnel barrier structure are assigned different thicknesses. The first tunnel barrier layer has greater thickness specifically where charge retention is critical, while the second tunnel barrier layer has lesser thickness where charge injection efficiency is prioritized.
3Reliability
If effective oxide thickness is increased to prevent charge back-migration, then data retention improves, but erase operation efficiency decreases
Solution Approach 1:
The insulative material is divided into two distinct layers: the first insulative layer with higher effective oxide thickness to prevent charge back-migration and ensure data retention, and the second insulative layer with lower effective oxide thickness to enable efficient erase operations by allowing charge removal.
Solution Approach 2:
Different regions of the insulative structure are assigned different effective oxide thicknesses. The first insulative layer has higher effective oxide thickness where charge retention is critical, while the second insulative layer has lower effective oxide thickness where erase operation efficiency is prioritized.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the effective oxide thickness to prevent charge leakage while enabling efficient removal of deeply-trapped charges during erase operations, thereby improving the operational characteristics of NAND memory cells.
Implementation Method 1
A charge-passage structure extends vertically along the insulative material. The charge-passage structure may comprise a central region sandwiched between a first region and a second region. The central region may have a lower probability of trapping charges and/or a lower rate of trapping charges
Implementation Method 2
a first tunnel barrier layer and a second tunnel barrier layer. The first tunnel barrier layer may have a greater thickness than the second tunnel barrier layer
Data Source
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AI summary
Some embodiments include a memory cell which has, in the following order; a control gate, charge-blocking material, charge- trapping material, a first oxide, a charge-passage structure, a second oxide, and channel material. The charge-passage structure has a central region sandwiched between first and second regions. The central region has a lower probability of trapping charges and/or a lower rate of trapping charges than the first and second regions. Some embodiments include an integrated structure having a vertical stack of alternating conductive levels and insulative levels, and having a charge-passage structure extending vertically along the vertical stack. Some embodiments include a NAN D memory array having a vertical stack of alternating insulative levels and wordline levels, and having a charge-passage structure extending vertically along the vertical stack.