Vertically-Spaced Charge Storage Segments in NAND Memory
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Solution Overview
Problem
Conventional NAND memory architectures face data retention issues due to charge migration between memory cells caused by charge-trapping material extending across multiple cells, leading to inefficiencies in charge storage and retrieval.
Innovation Solution
The introduction of breaks in the charge-trapping material between memory cells, combined with a vertical stack configuration of alternating insulative and conductive levels, where high-k dielectric material and charge-blocking layers are used to manage charge storage and prevent unwanted migration, forming vertically-spaced charge-storage segments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If charge-trapping material is used to store charge in NAND memory cells, then charge storage capability is improved, but charge migration between adjacent cells occurs causing data retention issues
Solution Approach 1:
The charge-blocking material is divided into vertically-spaced segments that are laterally offset relative to each other, creating discrete charge-blocking regions between memory cells. This segmentation prevents continuous charge migration paths while maintaining charge storage capability in the charge-trapping material.
Solution Approach 2:
The charge-blocking material acts as an intermediary barrier between adjacent memory cells, preventing direct charge migration while allowing the charge-trapping material to maintain its charge storage function. The segmented structure provides intermediate blocking regions that interrupt charge migration paths.
2Productivity
If continuous charge-trapping material is used across multiple memory cells, then charge storage efficiency is improved, but capacitive coupling between cells increases leading to charge migration
Solution Approach 1:
The charge-blocking material is segmented into vertically-spaced portions that are laterally offset, creating discrete blocking regions that reduce capacitive coupling between memory cells while allowing continuous charge-trapping material to maintain storage efficiency.
Solution Approach 2:
The charge-blocking segments are positioned with lateral offset in addition to vertical spacing, utilizing both vertical and lateral dimensions to create effective charge migration barriers. This multi-dimensional positioning reduces capacitive coupling more effectively than simple vertical spacing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively impedes charge migration between cells, enhancing data retention and operational efficiency by maintaining charge distribution and reducing capacitive coupling, thereby improving the overall performance of NAND memory arrays.
Implementation Method 1
high-k dielectric material and charge-blocking layers are used to manage charge storage and prevent unwanted migration
Data Source
AI summary
Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and second regions proximate to the control gate regions. High-k dielectric material wraps around ends of the control gate regions, and is not along the second regions. Charge-blocking material is adjacent to the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another by gaps. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.