3D NAND Charge-Storage Stack for Larger Memory Window
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Solution Overview
Problem
Current semiconductor devices face limitations in increasing data storage capacity and efficiency, particularly in achieving a larger memory window, improved endurance, and reduced operating voltage.
Innovation Solution
A semiconductor device is designed with a stack structure comprising interlayer insulating layers and gate electrodes alternately stacked, a channel layer within a hole, a data storage layer between the stack and channel layer, and dielectric layers between the data storage patterns and gate electrodes, using different materials for the data storage layer and patterns to enhance storage capacity and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional semiconductor device structure is used, then the device complexity is low, but the memory window is small and data storage capacity is limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking architecture. Multiple gate electrodes, interlayer insulating layers, data storage layers, and channel layers are stacked vertically to create memory cell strings that extend in the vertical dimension, thereby increasing data storage capacity without proportionally increasing device footprint area
Solution Approach 2:
The patent implements nested structures where channel layers are positioned inside holes penetrating through the stack structure, data storage layers surround the channel layers, and gate electrodes surround the data storage layers. This nested arrangement maximizes the use of vertical space and increases storage density within a compact volume
2Quantity of substance
If the memory window is increased using conventional methods, then data storage capacity improves, but the operating voltage increases
Solution Approach 1:
The patent changes material parameters by selecting specific dielectric materials with appropriate permittivity values for different layers (e.g., first dielectric material with higher permittivity than second dielectric material in some embodiments, or lower permittivity in others). This optimization of dielectric constants allows achieving larger memory windows through enhanced electric field control without requiring proportionally higher operating voltages
Solution Approach 2:
The patent employs composite dielectric structures with multiple layers having different material compositions and permittivity characteristics. The combination of different dielectric materials in the interlayer insulating layers and data storage layers creates a composite structure that optimizes both the memory window and the voltage required to achieve it
3Reliability
If conventional dielectric layers are used, then the manufacturing process is simple, but the endurance and retention characteristics are poor
Solution Approach 1:
The patent applies different dielectric materials with specific properties to different locations and layers within the device structure. The interlayer insulating layers and data storage layers use dielectric materials selected for their specific endurance and retention characteristics, while other regions may use different materials optimized for their local functions, thereby achieving high reliability without uniformly complicating the entire manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the memory window, improves endurance and retention characteristics, and lowers the operating voltage compared to related semiconductor devices, enabling more effective data storage and multibit operations.
Implementation Method 1
a first threshold voltage that causes a ferroelectric layer of the memory cell transistor to transition into a first polarization state, and a second threshold voltage that causes the ferroelectric layer to transition into a second polarization state
Data Source
AI summary
The present disclosure provides methods, apparatuses, and systems for operating and manufacturing a semiconductor device. In some embodiments, a semiconductor device includes a stack structure including interlayer insulating layers and gate electrodes, a channel layer disposed inside a hole penetrating through the stack structure, a data storage layer disposed between the stack structure and the channel layer, data storage patterns disposed between the data storage layer and the gate electrodes, and dielectric layers disposed between the data storage patterns and the gate electrodes. The interlayer insulating layers and the gate electrodes are alternately and repeatedly stacked in a first direction. A first material of the data storage layer is different from a second material of the data storage patterns.