Stacked NAND Memory Chip Bonding for Simpler Manufacturing
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Solution Overview
Problem
The manufacturing process of semiconductor memory devices, particularly NAND-type flash memory, is complex and inefficient, requiring improvements for cost-effectiveness and scalability.
Innovation Solution
A simplified manufacturing process for semiconductor memory devices involving a first chip with conductive layers, semiconductor layers, and insulating films, along with a second chip connected via electrodes, allowing for a more efficient assembly and integration of memory cell arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a traditional monolithic manufacturing process is used for NAND-type flash memory, then manufacturing precision and device reliability can be maintained, but the manufacturing process becomes excessively complex and productivity decreases
Solution Approach 1:
The patent divides the semiconductor memory device into multiple separate chips (first chip and second chip) that are manufactured independently and then bonded together. This segmentation allows each chip to be manufactured using simplified processes while maintaining the functionality of the complete device, thereby reducing overall manufacturing complexity and improving productivity.
2Device complexity
If multiple separate chips are bonded together to simplify manufacturing, then productivity improves and process complexity reduces, but manufacturing precision and device reliability may be compromised
Solution Approach 1:
The patent incorporates bonding pads and electrode structures on the chips before the bonding process. These preliminary structures are designed to guide and facilitate precise alignment during bonding, ensuring that the connection between chips achieves the required precision without compromising device reliability, while still maintaining the benefits of simplified manufacturing.
3Reliability
If chips are bonded with extensive electrode structures to ensure reliability, then device reliability improves, but the manufacturing process becomes more complex and costly
Solution Approach 1:
The patent extracts the bonding interface requirements into specific electrode structures and bonding pads that are incorporated into the chip designs. By taking out and standardizing these connection elements, the bonding process becomes more straightforward and reliable, improving ease of manufacture while ensuring device reliability through dedicated connection structures.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: a first chip including first conductive layers arranged at intervals in a first direction, a first semiconductor layer extending through an inside of the first conductive layers in the first direction, a first insulating film between the first semiconductor layer and the first conductive layers, a second semiconductor layer provided above the first conductive layers and in contact with the first semiconductor layer, and a first electrode provided in contact with an upper side of the second semiconductor layer; and a second chip including a second electrode in contact with the first electrode, and a second conductive layer in contact with the second electrode.