3D NAND Conductive Plug Floating Gate Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The fabrication of 3D NAND flash memory devices is complicated by the difficulty in performing ion implantation on mono-silicon/poly silicon conductive strips embedded in multi-layer stacks, leading to increased thermal budget and potential interference with erase/program operations.
Innovation Solution
A 3D memory device structure is developed, featuring a conductive stripe, memory layer, conductive pillar, and dielectric layer, where the conductive plug serves as a floating gate, reducing series resistance without ion implantation, and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion implantation is performed to dope mono-silicon/poly silicon conductive strips, then series resistance of cell strings is reduced, but manufacturing process complexity increases and thermal budget is significantly increased
Solution Approach 1:
The conductive strip is divided into two functional parts: an undoped region that maintains low resistance, and doped regions at specific locations (source/drain areas) that provide necessary electrical characteristics. This segmentation allows the conductive strip to achieve both low series resistance and proper device functionality without requiring full-length doping, thereby simplifying the manufacturing process while maintaining reliability.
2Reliability
If ion implantation is performed to dope conductive strips, then series resistance is reduced, but the process becomes nearly isotropic causing dopant diffusion in undesirable directions that may lead to device failure
Solution Approach 1:
The conductive strip is divided into undoped and doped regions, with the undoped segment maintaining low resistance and the doped segments providing localized electrical control. This spatial segmentation prevents isotropic dopant diffusion from affecting the entire strip, thereby maintaining manufacturing precision while achieving the desired electrical properties.
Solution Approach 2:
Different regions of the conductive strip are assigned different doping states: undoped regions for low resistance and doped regions for electrical control. This local quality differentiation allows precise control over dopant diffusion, ensuring that doping effects are confined to specific areas and do not propagate in undesirable directions, thus maintaining manufacturing precision.
3Reliability
If ion implantation process is added to fabricate 3D NAND flash memory device, then series resistance is reduced, but thermal budget is significantly increased
Solution Approach 1:
The conductive strip is segmented into undoped and doped regions, allowing the majority of the strip to remain undoped and thus avoid the high thermal budget associated with ion implantation. Only localized doped regions are created, significantly reducing the overall thermal exposure required during fabrication while maintaining the necessary electrical properties for device operation.
Data Source
AI summary
A memory device comprises a first conductive stripe, a first memory layer, a first conductive pillar, a first dielectric layer and a first conductive plug. The first conductive strip extends along a first direction. The first memory layer extends along a second direction adjacent to and overlapping with the first conductive stripe to define a first memory area thereon. The first conductive pillar extends along the second direction and overlapping with the first memory area. The first dielectric layer extends along the second direction adjacent to the first conductive stripe, the first memory layer and the first conductive pillar. The first conductive plus extends along the second direction and at least overlaps with a portion of the first conductive stripe, wherein the first conductive plus is electrically insulated from the first conductive stripe, the first memory layer and the first conductive pillar by the first dielectric layer.