3D NAND Decoder Layout for Low-Resistance Selection Lines
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Solution Overview
Problem
Nonvolatile memory devices face performance degradation due to increased resistance in string selection lines and complex wiring, especially in three-dimensional structures, which affect integration and efficiency.
Innovation Solution
The nonvolatile memory device employs a cell over periphery (COP) structure with address decoders driving different voltages on opposite sides of the cell region, utilizing first and second pass transistors in separate semiconductor layers to drive word-lines and selection lines, reducing resistance and simplifying wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional vertical NAND memory structure is used to increase integration degree and memory capacity, then memory capacity and integration degree are improved, but resistance in string selection lines increases and wiring becomes complex
Solution Approach 1:
The memory device is divided into two separate semiconductor layers: a first semiconductor layer containing the memory cell array with vertical NAND structures, and a second semiconductor layer containing the address decoders. This segmentation separates the high-density storage function from the control function, allowing the memory cell array to achieve high integration度和容量 while the address decoders in the separate layer manage the selection lines with reduced resistance through optimized transistor placement and shorter connection paths.
2Device complexity
If address decoders are integrated with the memory cell array in the same layer, then device complexity is reduced, but resistance in selection lines increases and performance degrades
Solution Approach 1:
The invention transitions from a planar two-dimensional layout to a three-dimensional stacked architecture where the first semiconductor layer (memory cell array) and second semiconductor layer (address decoders) are vertically stacked. This dimensional change allows the address decoders to be positioned directly beneath the memory cell array, creating short vertical connections for the selection lines that reduce resistance while maintaining organized wiring through the layered structure.
3Quantity of substance
If string selection lines are extended to cover larger memory regions, then memory capacity is increased, but resistance in the lines increases causing performance degradation
Solution Approach 1:
The address decoders in the second semiconductor layer act as intermediary control units that locally manage and drive the string selection lines before they extend to the memory cell array. By positioning the pass transistors in the address decoder layer close to the selection line origins, the invention creates an intermediate driving point that reduces the effective resistance along the extended selection lines, thereby maintaining performance reliability across larger memory capacities.
Data Source
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AI summary
A nonvolatile memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes word-lines, at least one string selection line, at least one ground selection line, and a memory cell array including at least one memory block. The second semiconductor includes a first address decoder and a second address decoder. The first address decoder is disposed under a first extension region adjacent to a first side of a cell region and includes a plurality of first pass transistors driving the word-lines, the at least one string selection line, and the at least one ground selection line. The second address decoder is disposed under a second extension region adjacent to a second side of the cell region and includes a plurality of second pass transistors driving the at least one string selection line and the at least one ground selection line.