3D NAND Flash Memory Digit Line Shielding and Segmentation
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Solution Overview
Problem
Conventional microelectronic device designs, particularly in 3D NAND Flash memory devices, face limitations in performance and feature size reduction due to the configuration of digit lines and logic circuitry, which hampers data transfer rates and increases power consumption.
Innovation Solution
The design incorporates local digit line structures and global digit line structures with a shielded configuration, where local digit lines are shorter and coupled to strings of memory cells, and global digit lines are longer, with read/write electrodes and source lines positioned to reduce parasitic capacitance and enhance read performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional digit line configurations are used, then the device structure is simpler, but data transfer rates deteriorate and power consumption increases
Solution Approach 1:
The digit line configuration is segmented into local digit lines coupled to memory cell strings and global digit lines extending to logic circuitry, with shield structures positioned between them. This segmentation allows optimization of each segment's function while reducing parasitic capacitance and improving data transfer rates without overwhelming complexity
Solution Approach 2:
Shield structures are introduced as intermediary elements positioned between local and global digit lines. These shields act as mediators that reduce parasitic capacitance and electromagnetic interference, enabling faster data transfer rates while maintaining a manageable device structure
2Area of stationary object
If digit line contacts are positioned at edges of the vertical memory array, then openings are provided to accommodate contacts, but this increases the horizontal footprint and reduces packaging density
Solution Approach 1:
The digit line contacts are repositioned from edge locations in the horizontal plane to positions above or below the vertical memory array in the vertical dimension. This dimensional change reduces the horizontal footprint and increases packaging density while maintaining manufacturability through standard vertical alignment processes
3Reliability
If conventional digit line configurations are used, then the device structure is simpler, but read performance deteriorates due to parasitic capacitance
Solution Approach 1:
Shield structures serve as intermediary elements positioned between local and global digit lines to reduce parasitic capacitance. These shields improve read performance by minimizing capacitive coupling while adding manageable structural complexity through standardized shield formation processes
Data Source
AI summary
A microelectronic device comprises local digit line structures, global digit line structures, source line structures, sense transistors, read transistors, and write transistors. The local digit line structures are coupled to strings of memory cells. The global digit line structures overlie the local digit line structures. The source line structures are interposed between the local digit line structures and the global digit line structures. The sense transistors are interposed between the source line structures and the global digit line structures, and are coupled to the local digit line structures and the source line structures. The read transistors are interposed between and are coupled to the sense transistors and the global digit line structures. The write transistors are interposed between and are coupled to the global digit line structures and the local digit line structures. Additional microelectronic devices, memory devices, and electronic systems are also described.