3D NAND Word Line Grounding via Dummy Lines to Shrink Chip Area
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Solution Overview
Problem
The increasing number of word lines in 3D NAND flash memory devices leads to a larger chip size due to the increased number of transistors required for driving these lines, which complicates the operating circuits and wiring structures.
Innovation Solution
The memory device reduces chip size by connecting ground transistors to dummy word lines instead of string select lines, thereby reducing the number of ground transistors in the ground transistor circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines is increased to increase memory capacity, then the storage capacity is improved, but the chip size increases due to the increased number of transistors
Solution Approach 1:
The patent divides the control structure into multiple segments: dummy word lines are introduced as intermediate control elements between string select lines and actual word lines. This segmentation allows ground transistors to be connected to dummy word lines rather than directly to string select lines, reducing the transistor count while maintaining control functionality for high-capacity memory blocks
Solution Approach 2:
Dummy word lines serve as intermediary control lines that mediate between the string select lines and the actual word lines. By connecting ground transistors to these intermediary dummy word lines instead of directly to string select lines, the patent reduces the number of ground transistors required while still enabling proper control of memory blocks with increased capacity
2Quantity of substance
If the number of pass transistors and ground transistors is increased to support more word lines, then the memory block capacity is improved, but the device complexity increases
Solution Approach 1:
The dummy word lines perform multiple functions: they serve as control lines for ground transistors, act as intermediaries for signal distribution, and enable scaling of memory block capacity without proportionally increasing transistor count. This multi-functionality reduces overall device complexity while supporting higher capacity
Solution Approach 2:
Instead of the conventional approach where ground transistors connect directly to string select lines, the patent inverts the connection structure by having ground transistors connect to dummy word lines, which are then controlled by string select lines. This inverted architecture reduces the number of ground transistors needed and simplifies the overall circuit structure
Data Source
AI summary
Memory devices in which ground transistors of string select lines are connected to a dummy word line to reduce a chip size are provided. In one aspect, the memory device includes a memory block including cell strings respectively selected by string select lines, where each cell string is connected to word lines stacked in a vertical direction, a pass transistor circuit including pass transistors respectively connected to the plurality of string select lines and the plurality of word lines, where the pass transistors are configured to be turned on based on the memory block being selected, and a ground transistor circuit including ground transistors respectively connected to word lines, where the ground transistors are configured to be turned on based on the memory block being unselected. A number of ground transistors is smaller than a number of string select lines.