3D NAND Memory Erase Control via Enhanced Verify Level
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Solution Overview
Problem
The incremental step pulse erase (ISPE) operation in 3D-NAND flash memory devices can cause deep erasure, leading to deteriorated wear performances and reliability, as well as increased programming time due to the lack of an erase inhibit function, which results in uneven threshold voltage distribution among memory cells.
Innovation Solution
A modified ISPE method is introduced, where an enhanced erase verify level is used to verify the erasure of memory cells, allowing for incremental adjustments in erase pulses to prevent deep erasure, maintaining wear performance while reducing erase time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a large ISPE step is used to reduce erase time, then erase time is reduced, but deep erasure occurs causing deteriorated wear performance and reliability
Solution Approach 1:
The patent changes the verification parameter by introducing an enhanced erase verify level (EV+) that is higher than the standard erase verify level (EV). This parameter change allows the use of larger ISPE steps while preventing deep erasure, as the enhanced verification level provides a safety margin that stops erasure before excessive depth is reached, thus resolving the contradiction between erase speed and reliability
Solution Approach 2:
The patent implements a feedback mechanism where an enhanced verification operation is performed after each erase pulse using the EV+ level. This feedback loop detects whether memory cells have reached the enhanced verify level and prevents further erasure of cells that have already passed the standard EV level, thereby preventing deep erasure while maintaining fast erase speeds through larger ISPE steps
2Loss of time
If a large ISPE step is used to reduce erase time, then erase time is reduced, but threshold voltage distribution becomes wider increasing programming time
Solution Approach 1:
By introducing and using the enhanced erase verify level (EV+) as a control parameter, the patent enables larger ISPE steps that complete erasure faster while the EV+ level itself acts as a cutoff that prevents threshold voltage distribution from becoming excessively wide, thus avoiding the need for extended programming time to correct over-erased cells
3Loss of time
If a high initial erase voltage is applied to maintain erase time, then erase time is maintained, but wear performance of memory cells is greatly affected
Solution Approach 1:
The patent segments the erasure process into two distinct verification stages: standard verification at EV level and enhanced verification at EV+ level. This segmentation allows the erasure process to proceed with high voltage for speed while the enhanced verification stage acts as a protective mechanism that prevents excessive wear by stopping erasure of cells that have already been sufficiently erased
Solution Approach 2:
The enhanced verification at EV+ level serves as a preliminary protective action before deep erasure can occur. By establishing this higher verification threshold in advance, the patent prevents memory cells from being subjected to excessive erasure voltage that would cause wear, while still allowing fast erase operation with large ISPE steps
Data Source
AI summary
In a method for erasing a memory device including memory cells, a first erase operation is performed on a selected memory cell of the memory cells. A first erase verifying operation is performed on the selected memory cell. A second erase verifying operation is performed on the selected memory cell. A second erase operation is performed on the selected memory cell based on results of the first erase verifying operation and the second erase verifying operation.