NAND Flash Bad Column Detection and Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
NAND flash memory arrays face inefficiencies in detecting and managing bad columns, leading to potential data errors and reduced reliability, as existing methods either replace entire chunks of columns or rely on memory controllers to handle bad columns coarsely, without distinguishing between column severity or providing precise column-level resolution.
Innovation Solution
A method and system for detecting bad columns at a column resolution, involving the generation of bad columns information, mapping data bits to specific flash memory cells, and applying error correction processes to determine and manage bad columns, allowing for bit skipping or replacement schemes to optimize data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If entire chunks of columns are replaced to manage bad columns, then reliability is improved, but device complexity and storage efficiency deteriorate due to coarse-grained replacement
Solution Approach 1:
The patent segments the bad column management into two distinct parts: (1) a bad column information storage structure that tracks individual bad columns at bit-level resolution, and (2) a replacement mechanism that operates at the granularity of individual bad columns rather than entire chunks. This segmentation allows precise identification and replacement of only the problematic columns while preserving the rest of the storage structure.
Solution Approach 2:
The patent applies local quality by treating each bad column individually with its own status information and replacement handling, rather than applying a uniform coarse-grained replacement policy to entire chunks. The bad column information structure stores specific status bits for individual columns, enabling differentiated management where only the affected local regions (specific bad columns) are replaced or marked, while the rest of the storage array remains fully operational.
2Productivity
If column-level resolution is used to detect bad columns, then productivity is improved through better storage utilization, but measurement precision requirements increase
Solution Approach 1:
The patent implements preliminary action by pre-allocating and pre-structuring the bad column information storage area before actual data storage operations begin. The status information for each column is prepared in advance, with predefined bit positions and structures ready to capture bad column identification data. This preliminary preparation enables efficient real-time detection and management of bad columns during normal storage operations without requiring complex on-the-fly analysis.
3Device complexity
If coarse-grained bad column handling is used, then device complexity is reduced, but loss of information increases due to inability to distinguish column severity
Solution Approach 1:
The patent applies parameter changes by transforming the bad column management from a binary good/bad classification to a multi-parameter status system. Each column's status information includes multiple bits that encode different aspects: whether the column is bad, the severity level, which specific bits are affected, and replacement status. This parameter expansion allows the system to maintain low complexity while preserving detailed information about column conditions, enabling nuanced decision-making for replacement and error correction strategies.
Data Source
AI summary
A system, computer readable medium and a method. The system includes a memory controller that comprises a control circuit and an interface. The memory controller is arranged to receive or generate bad columns information indicative of bad columns of the NAND flash memory array; wherein the bad columns information has a column resolution. The memory controller is arranged to receive an input data unit to be written to the NAND flash memory array; wherein the input data unit comprises bad column mapped data bits that are mapped to flash memory cells that belong to bad columns of the NAND flash memory array. The interface is arranged to send the input data unit to the NAND flash memory unit; instruct the NAND flash memory unit to write the input data unit to a first portion of the NAND flash memory array to provide a programmed data unit; send the bad column mapped data bits to the NAND flash memory unit; and instruct the NAND flash memory unit to write the bad column mapped data bits to a second portion of the NAND flash memory array to provide programmed bad column mapped data bits.