NAND Flash Bit Line Precharge Select Function for Verify Current Reduction
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Solution Overview
Problem
In NAND flash memory devices, the high consumed current during verify operations due to unnecessary charging of bit lines leads to increased read noise and inefficiency, especially as memory scales down, as the interference effects between locked-out and non-locked-out bit lines become more pronounced.
Innovation Solution
The implementation of a precharge select function (PCHSEL) that locks out and charges bit lines only for necessary memory cells, reducing unnecessary current consumption and minimizing interference by selectively charging bit lines corresponding to cells that require data writing, thereby maintaining consistent interference effects similar to read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit lines are charged for all memory cells during verify operations, then all memory cells can be verified, but unnecessary current consumption increases and read noise increases
Solution Approach 1:
The patent applies local quality by differentiating the treatment of bit lines based on whether they connect to memory cells requiring verification. Bit lines connected to cells needing verification are charged and used for reading, while bit lines connected to cells that have already been written to (and don't need verification) are locked out and not charged. This selective charging approach reduces unnecessary current consumption while maintaining complete verification capability for cells that need it.
Solution Approach 2:
The patent segments the bit line charging operation into two distinct groups: bit lines that are charged for verification operations and bit lines that are locked out. This segmentation is achieved through the precharge select function that identifies which bit lines should be charged based on the write target map, allowing independent control of charging operations for different bit line segments.
2Reliability
If bit lines are charged for all memory cells during verify operations, then all memory cells can be verified, but interference effects between locked-out and non-locked-out bit lines increase
Solution Approach 1:
The patent applies local quality by creating distinct electrical environments for different bit line groups. By locking out bit lines that don't need verification, the patent eliminates interference from unnecessary charging operations. The locked-out bit lines remain at a stable voltage level while only necessary bit lines undergo charging transients, thereby reducing interference effects between different bit line groups during verification.
3Use of energy by moving object
If precharge select function locks out bit lines, then unnecessary current consumption is reduced, but device complexity increases
Solution Approach 1:
The precharge select function serves multiple purposes: it identifies bit lines connected to write target cells, determines which bit lines should be charged during verification, and controls the locking out of unnecessary bit lines. By consolidating these functions into a single control mechanism that operates based on the write target map, the patent reduces overall device complexity while achieving the desired current reduction.
Data Source
AI summary
The semiconductor storage device of the embodiment includes memory cells. Word lines are connected to the memory cells. Bit lines are connected to the memory cells. A sense amplifier unit is connected to the bit lines. A data write operation includes a first write loop and a second write loop. The first write loop includes a first program operation and a first verify operation. The second write loop includes a second program operation and a second verify operation. A maximum value of a consumed current in the first verify operation is substantially equal to a maximum value of the consumed current in the second verify operation. The consumed current in the first verify operation is substantially same as the consumed current in the second verify operation if data input in the data write operation is all equal to first data corresponding to an erasure state.