NAND Flash Block Erase Control via Local Quality
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing NAND memory erase operations can cause cell stress, leading to degradation of memory characteristics, especially when different blocks have varying threshold voltage levels.
Innovation Solution
A semiconductor storage device with a control circuit that distinguishes between open and closed blocks during erase operations, adjusting the settings for erase-verify operations to reduce cell stress and ensure reliable erase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a unified erase-verify setting is applied to all blocks during erase operation, then the erase operation can be simplified and executed faster, but cell stress increases and erase reliability deteriorates for blocks with varying threshold voltage levels
Solution Approach 1:
The patent applies different erase-verify settings to different blocks based on their threshold voltage characteristics. Specifically, first erase-verify settings are applied to first blocks while second erase-verify settings are applied to second blocks, allowing each block to receive optimized treatment tailored to its specific characteristics rather than a one-size-fits-all approach.
Solution Approach 2:
The patent dynamically adjusts the erase-verify settings during the erase operation based on the block type. The control circuit determines whether to apply first or second erase-verify settings according to the specific block being erased, enabling adaptive optimization of the erase process for different block conditions while maintaining operational efficiency.
2Device complexity
If the erase-verify operation is performed with fixed settings for all blocks, then the control logic is simpler and execution is faster, but cell stress management and erase completeness are compromised
Solution Approach 1:
The patent implements local quality by applying different verify settings to different blocks. The control circuit identifies block types and applies first verify settings to some blocks and second verify settings to others, optimizing cell stress management for each block type while maintaining reasonable control complexity through systematic classification.
3Reliability
If different erase-verify settings are applied to different blocks, then erase reliability and cell stress management are improved, but the control complexity and operation time increase
Solution Approach 1:
The patent applies local quality principles by tailoring erase-verify settings to specific block characteristics. The control circuit determines whether to apply first or second verify settings based on block type, ensuring each block receives optimized treatment for its threshold voltage characteristics, thereby improving overall erase reliability through differentiated control.
Solution Approach 2:
The patent employs dynamic control by adaptively selecting different verify settings during the erase operation. The control circuit dynamically adjusts the verify parameters based on the specific block being processed, enabling optimized cell stress management and erase reliability while maintaining operational efficiency through systematic adaptation rather than static configuration.
Data Source
AI summary
A semiconductor storage device of embodiments includes a block constituted with a plurality of strings each including a plurality of memory cell transistors, a plurality of word lines, a bit line, a source line, and a control circuit configured to perform erase operation on the plurality of memory cell transistors, and the control circuit changes setting of first erase-verify operation included in the erase operation for an open block including a memory cell transistor having an erase level and setting of second erase-verify operation included in erase operation for a closed block not including a memory cell transistor having an erase block.