NAND Flash Error Correction for Burst and Periodic Read Errors

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Solution Overview

Problem

Existing error correction methods in NAND flash memory systems struggle to correct burst and periodic errors, which can cause decoding failures despite the error correction code's correction limit not being exceeded, as the error patterns are non-random and difficult to identify.

Innovation Solution

An error correction device and method that includes a burst error check circuit and a periodic error check circuit to detect and specify these error patterns, followed by a data rewrite circuit to modify the data based on suspected error positions, allowing for re-decoding attempts to accurately identify and correct errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional error correction decoding is performed on read data from NAND flash memory, then random errors within the correction limit can be corrected, but burst errors and periodic errors cause decoding failures even when the error count is within the correction limit

Engineering Contradiction:
Improveerror correction capabilityVSAvoiderror pattern recognition
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent segments the error detection process into multiple specialized circuits: a burst error check circuit that divides data into segments to detect consecutive errors, and a periodic error check circuit that identifies repeating error patterns. This segmentation allows the system to handle different error types independently, resolving the contradiction between maintaining high reliability for random errors and gaining adaptability for burst and periodic errors.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediary error detection circuits that act as mediators between the read data and the main error correction decoder. These circuits (burst error check circuit and periodic error check circuit) preprocess the data to identify specific error patterns, enabling the main decoder to focus on correcting errors rather than detecting pattern types, thus improving both reliability and adaptability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If the error correction code's correction limit is exceeded due to burst or periodic errors, then decoding fails, but standard error correction methods cannot identify these non-random error patterns

Engineering Contradiction:
Improveerror detection accuracyVSAvoiderror detection mechanism
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by designing specialized detection mechanisms for specific error locations and patterns. The burst error check circuit focuses on detecting consecutive errors in localized segments, while the periodic error check circuit targets repeating patterns at specific intervals. This localized approach improves measurement precision for different error types without requiring a complete redesign of the entire error correction system, thus managing device complexity effectively.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent performs preliminary error pattern detection before main error correction decoding. The burst error check circuit and periodic error check circuit analyze the read data in advance to identify error patterns, allowing the system to prepare appropriate correction strategies beforehand. This preliminary action improves detection accuracy by focusing computational resources on identifying error patterns before the main correction process begins.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If multiple decoding attempts are performed with rewritten data, then burst and periodic errors can be corrected, but processing time increases

Engineering Contradiction:
Improvedecoding success rateVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent employs periodic action through iterative decoding attempts with rewritten data. When burst or periodic errors are detected, the system performs multiple decoding cycles, each time rewriting suspected error bits and attempting decoding again. This periodic retry mechanism increases the decoding success rate for difficult error patterns while managing processing time by stopping after a predetermined number of attempts, thus balancing reliability and time loss.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent implements feedback loops where the results of each decoding attempt are used to guide subsequent rewriting and re-decoding operations. The error detection circuits provide feedback about detected patterns, and the decoding success or failure feeds back into the rewriting strategy. This feedback mechanism improves reliability by learning from previous attempts while optimizing processing time by avoiding redundant operations based on accumulated information.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20260074006A1Error correction device, error correction method, and semiconductor memory system
Publication Date: 2026.03.12 KIOXIA CORP
  • US20260074006A1 patent drawing
  • US20260074006A1 patent drawing
  • US20260074006A1 patent drawing

AI summary

According to some embodiments, an error correction device includes a decoding circuit configured to read out user data encoded with an error correction code from a nonvolatile memory and perform error correction decoding based on the error correction code on read data of a size, and a rewrite circuit configured to rewrite one or more bits in the read data of the size. The one or more bits include M consecutive bits or a plurality of bits at N-bit intervals. M is a natural number equal to or greater than 1, and N is a natural number equal to or greater than 1.