NAND Flash Charge Storage Pattern Uniformity
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Solution Overview
Problem
NAND flash memory devices face challenges in achieving high coupling ratios and uniform thickness of floating gate patterns, leading to increased parasitic capacitance and operation failures due to non-uniform thickness and interference between neighboring cells.
Innovation Solution
A method involving the formation of a mold pattern on a substrate, followed by selective deposition of a preliminary pattern using PVD or CVD processes, and subsequent removal to achieve a uniform and thinner charge storage pattern, with a thickness of 20 Å to 500 Å, to reduce parasitic capacitance and enhance integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the floating gate pattern is formed with a large line width to increase capacitance between floating gate and control gate, then the coupling ratio is improved, but the degree of integration decreases due to larger gap distance required between unit cells
Solution Approach 1:
The patent transitions from controlling capacitance through lateral dimensions (line width) to controlling it through vertical dimension (dielectric layer thickness). By making the dielectric layer thinner, the electrical field strength increases, thereby increasing capacitance without requiring larger floating gate line widths, thus maintaining high integration density while achieving sufficient coupling ratio.
Solution Approach 2:
The patent changes the thickness parameter of the dielectric layer to control the electrical characteristics. By reducing the dielectric layer thickness from conventional values to a thinner range, the capacitance between floating gate and control gate is increased, allowing for smaller floating gate dimensions and higher integration without sacrificing coupling ratio.
2Area of moving object
If the floating gate pattern is formed with a small gap distance to increase degree of integration, then the surface area is reduced, but parasitic capacitance between neighboring floating gate patterns increases causing interference between unit cells
Solution Approach 1:
The patent addresses parasitic capacitance by controlling the vertical dimension (dielectric layer thickness) rather than lateral spacing. The thinner dielectric layer creates a stronger electrical field that is more confined, reducing the lateral spread of electrical fields and thus minimizing parasitic coupling between adjacent floating gates even when they are closely spaced.
3Reliability
If a conventional dielectric layer with multilayer structure is used to increase capacitance, then the coupling ratio is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by using a single-layer dielectric structure with uniformly distributed high-k material throughout the layer, rather than stacking multiple layers with different materials. This provides the necessary capacitance enhancement through the bulk properties of the high-k material, simplifying the structure while maintaining electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables the formation of non-volatile memory devices with improved coupling ratios, reduced parasitic capacitance, and increased operation reliability by achieving uniform thickness across the substrate, thereby enhancing the integration and performance of NAND flash memory devices.
Implementation Method 1
selective deposition of a preliminary pattern using PVD or CVD processes
Implementation Method 2
selective deposition of a preliminary pattern using PVD or CVD processes
Implementation Method 3
A tunnel oxide layer may be formed on the substrate in the opening
Data Source
AI summary
A method of forming a semiconductor device pattern, a method of forming a charge storage pattern, a non-volatile memory device including a charge storage pattern and a method of manufacturing the same are provided. The method of forming the charge storage pattern including forming a trench on a substrate, and a device isolation pattern in the trench. The device isolation pattern protrudes from a surface of the substrate such that an opening exposing the substrate is formed. A tunnel oxide layer is formed on the substrate in the opening. A preliminary charge storage pattern is formed on the tunnel oxide layer and the device isolation pattern by selective deposition of conductive materials. The preliminary charge storage pattern may be removed from the device isolation pattern. The preliminary charge storage pattern remains only on the tunnel oxide layer to form the charge storage pattern on the substrate.