NAND Flash Memory Controller Er State Elimination

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Solution Overview

Problem

Current memory systems using NAND flash memory face challenges in efficiently reading and writing data without using the 'Er' state, leading to fluctuations in threshold voltage distributions and errors in data retrieval, especially when the 'Er' state overlaps with other states, making it difficult to determine optimal reading voltages and maintaining data reliability.

Innovation Solution

The memory system employs a controller circuit that uses k reading voltages different from each other to determine n-bit data, converts the data into (k+1) decimal data, and performs a tracking operation to adjust the threshold voltage distribution, ensuring data is written and read without using the 'Er' state, thereby maintaining data reliability and reducing errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the Er state is used for data storage in NAND flash memory, then the memory capacity is increased, but the threshold voltage distribution becomes overlapping and data reliability deteriorates

Engineering Contradiction:
Improvememory capacityVSAvoiddata reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent extracts and removes the problematic 'Er' state from the threshold voltage distribution. By defining read voltages that specifically exclude the Er state region and only utilize the A, B, and C states for data storage and retrieval, the invention eliminates the source of threshold voltage overlap and reliability issues while preserving the multi-level cell capacity.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the threshold voltage distribution into distinct, non-overlapping regions. By creating clear boundaries between the A, B, and C states and excluding the Er state from data storage operations, the invention divides the voltage spectrum into separable zones that can be reliably read without interference or overlap.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If multiple reading voltages are used to determine n-bit data, then the data accuracy is improved, but the reading operation complexity increases

Engineering Contradiction:
Improvedata accuracyVSAvoidreading operation complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent changes the parameters of the reading operation by defining specific read voltages (Vread1, Vread2, Vread3) that correspond to the A, B, and C states. By optimizing these voltage parameters to align with the distinct threshold voltage regions and excluding the Er state, the invention achieves high data accuracy while maintaining manageable operational complexity through systematic voltage sequencing.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If the tracking operation is performed to adjust threshold voltage distribution, then the data reliability is improved, but the processing time is increased

Engineering Contradiction:
Improvedata reliabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary tracking operations during the write process to pre-adjust the threshold voltage distribution before read operations. By conducting the tracking action in advance and establishing the A, B, and C state distributions prior to data retrieval, the invention reduces the time required during actual read operations while maintaining high data reliability.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10714171B2NAND flash memory system storing multi-bit data and read/write control method thereof
Publication Date: 2020.07.14 KIOXIA CORP
  • US10714171B2 patent drawing
  • US10714171B2 patent drawing
  • US10714171B2 patent drawing

AI summary

According to one embodiment, a memory system comprising: a semiconductor storage device including a memory cell connected to a word line and capable of storing n-bit data (n is an integer of 2 or more); and a controller circuit, wherein the semiconductor storage device determines a value of the n-bit read data stored in the memory cell, by a first reading operation using k reading voltages different from each other (k is an integer equal to or higher than 2{circumflex over ( )}(n−1) and less than 2{circumflex over ( )}n−1), and the controller circuit converts the value of the n-bit read data into data corresponding to (k+1) decimal data.