NAND Flash Distributed Virtual Cache Architecture
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Solution Overview
Problem
Current non-volatile memory devices, such as NAND flash memory, face performance limitations due to the use of volatile memory in controllers, which increases costs and reduces efficiency in random programming operations.
Innovation Solution
Implementing a distributed virtual cache architecture within NAND flash memory devices using separate registers for read and programming operations, allowing for interleaved operations and data swapping between cache and data registers to optimize performance without increasing volatile memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If volatile memory is used in controllers of managed memory devices, then data buffering and operation translation can be performed, but the area consumption increases and controller costs increase
Solution Approach 1:
The patent extracts the volatile memory buffer function from the external controller and relocates it to the NAND flash memory device itself by repurposing the data register as a distributed virtual cache. This eliminates the need for volatile memory in the controller while maintaining the data buffering capability, directly resolving the contradiction between productivity and area consumption.
Solution Approach 2:
The data register in the NAND flash memory device is given multiple functions: it serves as both the traditional data register for programming operations and as a distributed virtual cache for buffering data. This multi-functionality allows the system to maintain buffering capabilities without adding dedicated volatile memory, addressing the contradiction between productivity and area usage.
2Productivity
If separate registers are used for read and programming operations, then random programming performance is improved, but device complexity increases
Solution Approach 1:
The patent segments the data register into multiple independent banks (e.g., four 512-byte banks). This segmentation allows simultaneous read and programming operations to occur in parallel across different banks, improving random programming performance while keeping the overall architecture manageable through modular design.
Solution Approach 2:
The patent introduces a new dimension to the register architecture by organizing data banks in a two-dimensional array structure with row and column addressing. This dimensional organization enables efficient simultaneous access patterns for both read and programming operations without significantly increasing control logic complexity.
3Productivity
If data is swapped between cache register and data register, then interleaved operations can be performed, but control complexity increases
Solution Approach 1:
The patent implements preliminary action by pre-organizing data into separate banks within the data register before operations begin. This pre-organization allows the controller to perform interleaved read and programming operations without complex real-time data movement logic, as the data is already positioned for efficient access.
Solution Approach 2:
The patent introduces a bank address counter and control logic that acts as an intermediary between the controller and the data banks. This intermediary automatically manages the swapping and selection of data banks during interleaved operations, simplifying the control complexity by encapsulating the complexity in a dedicated control module rather than distributing it throughout the system.
Data Source
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AI summary
In some embodiments, one register of a non-volatile memory can be used for read operations and another register of the non-volatile memory can be used for programming operations. For instance, a cache register of a NAND flash memory can be used in connection with read operations and a data register of the NAND flash memory can be used in connection with programming operations. Data registers of a plurality of non-volatile memory devices, such as NAND flash memory devices, can implement a distributed volatile cache (DVC) architecture in a managed memory device, according to some embodiments. According to certain embodiments, data can be moved and/or swapped between registers to perform certain operations in the non-volatile memory devices without losing the data stored while other operations are performed.